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| copyright ? 2010-2011 fujitsu semiconductor limited all rights reserved 2011.1 fujitsu semiconductor data sheet ds706-00007-1v0-e fujitsu semiconductor confidential r2.1 32-bit arm tm cortex tm -m3 based microcontroller fm3 mb9b100 series mb9bf104n/r, f105n/r, f106n/r ? description the mb9b100 series are a highly integrated 32-bit mi crocontroller that target for high-performance and cost-sensitive embedded control applications. the mb9b100 series are based on the arm cortex-m3 processor and on-chip flash memory and sram, and peripheral functions, including motor control timers, adcs and communication interfaces (uart, sio, i 2 c, lin). note: arm and cortex-m3 are the trademarks of arm limited in the eu and other countries.
mb9b100 series ? features ? 32-bit arm cortex-m3 core ? processor version: r2p0 ? up to 80mhz frequency operation ? memory protection unit (mpu): improve the reliability of an embedded system ? integrated nested vectored interrupt controller (nvic): 1 nmi (non-maskable interrupt) and 48 peripheral interrupts and 16 priority levels ? 24-bit system timer (sys tick): system timer for os task management ? on-chip memories [flash memory] ? up to 512 kbyte ? read cycle: 0wait-cycle@up to 60mhz, 2wait-cycle* above *: instruction pre-fetch buffer is included. so when cpu access continuous ly, it becomes 0wait-cycle ? security function for code protection [sram] mb9b100 series contain a total of up to 64kbyte on-chip sram memories. this is composed of two independent sram for cpu and dma controller can process simultaneously. ? up to 32 kbyte sram for high-performance cpu ? up to 32 kbyte sram for cpu/dma controller ? external bus interface ? supports sram, nor& nand flash device ? up to 8 chip selects ? 8/16-bit data width ? up to 25-bit address bit ? multi-function serial interface (max. 8channels) ? 4 channels with 16-byte fifo (ch.4-ch.7 ), 4 channels without fifo (ch.0-ch.3) ? operation mode is selectable from the followings for each channel. ? uart ? csio ? lin ? i 2 c [uart] ? full-duplex double buffer ? selection with or without parity supported ? built-in dedicated baud rate generator ? external clock available as a serial clock ? hardware flow control : automatically contro l the transmission by cts/rts (only ch.4) ? various error detect functions available (parit y errors, framing errors, and overrun errors) [csio] ? full-duplex double buffer ? built-in dedicated baud rate generator ? overrun error detect function available 2 fujitsu semiconductor confidential r2.1 ds706-00007-1v0-e mb9b100 series [lin] ? lin protocol rev.2.1 supported ? full-duplex double buffer ? master/slave mode supported ? lin break field generate (can be changed 13-16bit length) ? lin break delimiter generate (can be changed 1-4bit length) ? various error detect functions available (parit y errors, framing errors, and overrun errors) [i 2 c] ? standard mode (max.100kbps) / high-speed mode (max.400kbps) supported ? dma controller (8channels) dma controller has an independent bus for cpu, so cpu and dma controller can process simultaneously. ? 8 independently configured and operated channels ? transfer can be started by software or request from the built-in peripherals ? transfer address area: 32bit(4gbyte) ? transfer mode: block transfer/burst transfer/demand transfer ? transfer data type: byte/half-word/word ? transfer block count: 1 to 16 ? number of transfers: 1 to 65536 ? a/d converter (max. 16channels) [12-bit a/d converter] ? successive approximation register type ? built-in 3unit ? conversion time: 1.0 s@5v ? priority conversion availa ble (priority at 2levels) ? scanning conversion mode ? built-in fifo for conversion data storage (for scan conversion: 16 steps, for priority conversion: 4steps) ? base timer (max. 8channels) operation mode is selectable from the followings for each channel. ? 16-bit pwm timer ? 16-bit ppg timer ? 16/32-bit reload timer ? 16/32-bit pwc timer ? general purpose i/o port mb9b100 series can use its pins as i/o ports when th ey are not used for external bus or peripherals. moreover, the port relocate function is built in. it can set which i/o port the peripheral function can be allocated. ? capable of pull-up control per pin ? capable of reading pin level directly ? built-in the port relocate function ? up to 100 fast i/o ports@120pin package 3 fujitsu semiconductor confidential r2.1 ds706-00007-1v0-e mb9b100 series ? multi-function timer (max. 2unit) the multi-function timer is composed of the following blocks. ? 16-bit free-run timer 3ch/unit ? input capture 4ch/unit ? output compare 6ch/unit ? a/d activating compare 3ch/unit ? waveform generator 3ch/unit ? 16-bit ppg timer 3ch/unit the following function can be used to achieve the motor control. ? pwm signal output function ? dc chopper waveform output function ? dead time function ? input capture function ? a/d convertor activate function ? dtif (motor emergency stop) interrupt function ? quadrature position/revolution counter (qprc) (max. 2unit) the quadrature position/revolution counter (qprc) is used to measure the position of the position encoder. moreover, it is possible to use up/down counter. ? the detection edge of the three external event input pins ain, bin and zin is configurable. ? 16-bit position counter ? 16-bit revolution counter ? two 16-bit compare registers ? dual timer (two 32/16bit down counter) the dual timer consists of two programmable 32/16-bit down counters. operation mode is selectable from the followings for each channel. ? free-running ? periodic (=reload) ? one-shot ? watch counter the watch counter is used for wake up from power saving mode. ? interval timer: up to 64s(max.)@ sub clock : 32.768khz ? external interrupt controller unit ? up to 16 external vectors ? include one non-maskable interrupt(nmi) ? watch dog timer (2channels) a watchdog timer can generate interrupts or a reset when a time-out value is reached. mb9b100 series consists of two different watchdogs, a "hardware" watchdog an d a "software" watchdog. "hardware" watchdog timer is clocked by low spee d cr oscillator. therefore, ?hardware" watchdog is active in any power saving mode except stop. 4 fujitsu semiconductor confidential r2.1 ds706-00007-1v0-e mb9b100 series ? crc (cyclic redundancy check) accelerator the crc accelerator helps a verify data transmission or storage integrity. ccitt crc16 and ieee-802.3 crc32 are supported. ? ccitt crc16 generator polynomial: 0x1021 ? ieee-802.3 crc32 generator polynomial: 0x04c11db7 ? clock and reset [clocks] five clock sources (2 ext. osc, 2 cr osc, and pll) that are dynamically selectable. ? main clock : 4 to 48mhz ? sub clock : 32.768khz ? high-speed cr clock : 4mhz ? low-speed cr clock : 100khz ? pll clock [resets] reset requests from initx pins, power on reset, so ftware reset, watchdog timers reset, low voltage detector reset and clock supervisor reset. ? clock super visor (csv) clocks generated by cr oscillators are used to supervise abnormality of the external clocks. ? external osc clock failure (clock st op) is detected, reset is asserted. ? external osc frequency anomaly is detected, interrupt or reset is asserted. ? low voltage detector (lvd) mb9b100 series include 2-stage monitoring of voltage on the vcc. when the voltage falls below the voltage has been set, low voltage detector generates an interrupt or reset. ? lvd1: error reporting via interrupt ? lvd2: auto-reset operation ? low power mode three power saving modes supported. ? sleep ? timer ? stop ? debug ? serial wire jtag debug port (swj-dp) ? embedded trace macrocells (etm) provide comprehensive debug and trace facilities. ? trace port interface unit (t piu) for bridging to a trace port analyzer. ? power supply two power supplies ? vcc = 2.7v to 5.5v: correspond to the wide range voltage. 5 fujitsu semiconductor confidential r2.1 ds706-00007-1v0-e mb9b100 series ? product lineup ? memory size product device mb9bf104n/r mb9bf105n/r mb9bf106n/r on-chip flash 256kbyte 384kbyte 512kbyte on-chip ram 32kbyte 48kbyte 64kbyte ? function product device mb9bf104n mb9bf105n mb9bf106n mb9bf104r mb9bf105r mb9bf106r pin count 100 120 cortex-m3 cpu freq. 80mhz power supply voltage range 2.7v to 5.5v dmac 8ch external bus interface addr:25bit (max.) data:8/16 bit cs:5(max.) support:sram, nor flash addr:25bit (max.) data:8/16 bit cs:8(max.) support:sram, nor & nand flash mf serial interface (uart/csio/lin/i 2 c) 8ch (max.) base timer (pwc/reload timer/pwm/ppg) 8ch (max.) a/d activation compare 3ch input capture 4ch free-run timer 3ch output compare 6ch waveform generator 3ch mf- timer ppg 3ch 2 units (max.) qprc 2ch (max.) dual timer 1 unit watch counter 1 unit crc accelerator yes watchdog timer 1ch(sw) + 1ch(hw) external interrupts 16pins (max.)+ nmi 1 i/o ports 80pins (max.) 100pins (max.) 12 bit a/d converter 16ch (3 units) csv (clock super visor) yes lvd (low voltage detector) 2ch high-speed 4mhz ( 2%) internal osc low-speed 100khz (typ) debug function swj-dp/tpiu/etm note: all signals of the peripheral function in each product cannot be allocated by limiting the pins of package. it is necessary to use the port relocate function of the general i/o port according to your function use. 6 fujitsu semiconductor confidential r2.1 ds706-00007-1v0-e 7 fujitsu semiconductor confidential r2.1 mb9b100 series ? packages product name package mb9bf104n mb9bf105n mb9bf106n mb9bf104r mb9bf105r mb9bf106r lqfp: fpt-100p-m20*/m23 ? - lqfp: fpt-120p-m21 - ? bga: bga-112p-m04 ? - ?? : supported * : es product only note : refer to " ? package dimensions" for detailed information on each package. ds706-00007-1v0-e mb9b100 series ? pin assignment ? fpt-100p-m20/m23 (top view) mb9b100 series ? fpt-120p-m21 (top view) mb9b100 series ? bga-112p-m04 11 fujitsu semiconductor confidential r2.0 mb9b100 series ? pin description the number after the underscore ("_") in pin name s such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin. pin no. lqfp-100 bga-112 lqfp-120 pin name i/o circuit type pin state type 1 b1 1 vcc - p50 int00_0 ain0_2 sin3_1 rto10_0 (ppg10_0) 2 c1 2 mdata0 e h p51 int01_0 bin0_2 sot3_1 (sda3_1) rto11_0 (ppg10_0) 3 c2 3 mdata1 e h p52 int02_0 zin0_2 sck3_1 (scl3_1) rto12_0 (ppg12_0) 4 b3 4 mdata2 e h p53 sin6_0 tioa1_2 int07_2 rto13_0 (ppg12_0) 5 d1 5 mdata3 e h p54 sot6_0 (sda6_0) tiob1_2 rto14_0 (ppg14_0) 6 d2 6 mdata4 e i ds706-00007-1v0-e mb9b100 series pin no. lqfp-100 bga-112 lqfp-120 pin name i/o circuit type pin state type p55 sck6_0 (scl6_0) adtg_1 rto15_0 (ppg14_0) 7 d3 7 mdata5 e i p56 sin1_0 (120pin only) int08_2 dtti1x_0 8 d5 8 mcsx7 e h p57 sot1_0 (sda1_0) - - 9 mnale e i p58 sck1_0 (scl1_0) - - 10 mncle e i p59 sin7_0 int09_2 - - 11 mnwex e h p5a sot7_0 (sda7_0) - - 12 mnrex e i p5b - - 13 sck7_0 (scl7_0) e i p30 ain0_0 tiob0_1 int03_2 9 e1 14 mdata6 e h 12 fujitsu semiconductor confidential r2.0 ds706-00007-1v0-e mb9b100 series pin no. lqfp-100 bga-112 lqfp-120 pin name i/o circuit type pin state type p31 bin0_0 tiob1_1 sck6_1 (scl6_1) int04_2 10 e2 15 mdata7 e h p32 zin0_0 tiob2_1 sot6_1 (sda6_1) int05_2 11 e3 16 mdqm0 e h p33 int04_0 tiob3_1 sin6_1 adtg_6 12 e4 17 mdqm1 e h p34 frck0_0 tiob4_1 13 f1 18 mad24 e i p35 ic03_0 tiob5_1 int08_1 14 f2 19 mad23 e h p36 ic02_0 sin5_2 int09_1 15 f3 20 mcsx3 e h p37 ic01_0 sot5_2 (sda5_2) int10_1 16 g1 21 mcsx2 e h p38 ic00_0 sck5_2 (scl5_2) 17 g2 22 int11_1 e h 13 fujitsu semiconductor confidential r2.0 ds706-00007-1v0-e mb9b100 series pin no. lqfp-100 bga-112 lqfp-120 pin name i/o circuit type pin state type p39 dtti0x_0 18 f4 23 adtg_2 e i p3a rto00_0 (ppg00_0) 19 g3 24 tioa0_1 g i - b2 - vss - p3b rto01_0 (ppg00_0) 20 h1 25 tioa1_1 g i p3c rto02_0 (ppg02_0) 21 h2 26 tioa2_1 g i p3d rto03_0 (ppg02_0) 22 g4 27 tioa3_1 g i p3e rto04_0 (ppg04_0) 23 h3 28 tioa4_1 g i p3f rto05_0 (ppg04_0) 24 j2 29 tioa5_1 g i 25 l1 30 vss - 26 j1 31 vcc - p40 tioa0_0 rto10_1 (ppg10_1) int12_1 27 j4 32 mad22 g h p41 tioa1_0 rto11_1 (ppg10_1) int13_1 28 l5 33 mad21 g h 14 fujitsu semiconductor confidential r2.0 ds706-00007-1v0-e mb9b100 series pin no. lqfp-100 bga-112 lqfp-120 pin name i/o circuit type pin state type p42 tioa2_0 rto12_1 (ppg12_1) 29 k5 34 mad20 g i p43 tioa3_0 rto13_1 (ppg12_1) adtg_7 30 j5 35 mad19 g i - k2 - vss - - j3 - vss - - h4 - vss - p44 tioa4_0 rto14_1 (ppg14_1) 31 h5 36 mad18 g i p45 tioa5_0 rto15_1 (ppg14_1) 32 l6 37 mad17 g i 33 l2 38 c - 34 l4 39 vss - 35 k1 40 vcc - p46 36 l3 41 x0a d m p47 37 k3 42 x1a d n 38 k4 43 initx b c p48 dtti1x_1 int14_1 sin3_2 39 k6 44 mad16 e h p49 tiob0_0 ic10_1 ain0_1 sot3_2 (sda3_2) 40 j6 45 mad15 e i 15 fujitsu semiconductor confidential r2.0 ds706-00007-1v0-e mb9b100 series pin no. lqfp-100 bga-112 lqfp-120 pin name i/o circuit type pin state type p4a tiob1_0 ic11_1 bin0_1 sck3_2 (scl3_2) 41 l7 46 mad14 e i p4b tiob2_0 ic12_1 zin0_1 42 k7 47 mad13 e i p4c tiob3_0 ic13_1 sck7_1 (scl7_1) ain1_2 43 h6 48 mad12 e i p4d tiob4_0 frck1_1 sot7_1 (sda7_1) bin1_2 44 j7 49 mad11 e i p4e tiob5_0 int06_2 sin7_1 zin1_2 45 k8 50 mad10 e i p70 - - 51 tioa4_2 e i p71 int13_2 - - 52 tiob4_2 e h p72 sin2_0 - - 53 int14_2 e h 16 fujitsu semiconductor confidential r2.0 ds706-00007-1v0-e mb9b100 series pin no. lqfp-100 bga-112 lqfp-120 pin name i/o circuit type pin state type p73 sot2_0 (sda2_0) - - 54 int15_2 e h p74 - - 55 sck2_0 (scl2_0) e i 46 k9 56 md1 c d 47 l8 57 md0 c d 48 l9 58 x0 a a 49 l10 59 x1 a b 50 l11 60 vss - 51 k11 61 vcc - p10 52 j11 62 an00 f k p11 an01 sin1_1 53 j10 63 int02_1 f l - k10 - vss - - j9 - vss - p12 an02 sot1_1 (sda1_1) 54 j8 64 mad09 f k p13 an03 sck1_1 (scl1_1) 55 h10 65 mad08 f k p14 an04 sin0_1 int03_1 56 h9 66 mcsx1 f l p15 an05 sot0_1 (sda0_1) 57 h7 67 mcsx0 f k 17 fujitsu semiconductor confidential r2.0 ds706-00007-1v0-e mb9b100 series pin no. lqfp-100 bga-112 lqfp-120 pin name i/o circuit type pin state type p16 an06 sck0_1 (scl0_1) 58 g10 68 moex f k p17 an07 sin2_2 int04_1 59 g9 69 mwex f l 60 h11 70 avcc - 61 f11 71 avrh - 62 g11 72 avss - p18 an08 sot2_2 (sda2_2) 63 g8 73 mdata8 f k p19 an09 sck2_2 (scl2_2) 64 f10 74 mdata9 f k p1a an10 sin4_1 int05_1 ic00_1 65 f9 75 mdata10 f l - h8 - vss - p1b an11 sot4_1 (sda4_1) ic01_1 66 e11 76 mdata11 f k p1c an12 sck4_1 (scl4_1) ic02_1 67 e10 77 mdata12 f k 18 fujitsu semiconductor confidential r2.0 ds706-00007-1v0-e mb9b100 series pin no. lqfp-100 bga-112 lqfp-120 pin name i/o circuit type pin state type p1d an13 cts4_1 ic03_1 68 f8 78 mdata13 f k p1e an14 rts4_1 dtti0x_1 69 e9 79 mdata14 f k p1f an15 adtg_5 frck0_1 70 d11 80 mdata15 f k p28 adtg_4 rto05_1 (ppg04_1) - - 81 mcsx6 e i p27 int02_2 rto04_1 (ppg04_1) - - 82 mcsx5 e h p26 sck2_1 (scl2_1) rto03_1 (ppg02_1) - - 83 mcsx4 e i p25 sot2_1 (sda2_1) - - 84 rto02_1 (ppg02_1) e i - b10 - vss - - c9 - vss - p24 sin2_1 int01_2 - - 85 rto01_1 (ppg00_1) e h 19 fujitsu semiconductor confidential r2.0 ds706-00007-1v0-e mb9b100 series pin no. lqfp-100 bga-112 lqfp-120 i/o circuit pin state type pin name type p23 sck0_0 (scl0_0) tioa7_1 71 d10 86 rto00_1 (ppg00_1) e i p22 sot0_0 (sda0_0) tiob7_1 72 e8 87 e i zin1_1 p21 sin0_0 int06_1 73 c11 88 bin1_1 e h p20 int05_0 crout 74 c10 89 ain1_1 e h 75 a11 90 vss - 76 a10 91 vcc - p00 77 a9 92 trstx e e p01 tck 78 b9 93 swclk e e p02 79 b11 94 tdi e e p03 tms 80 a8 95 swdio e e p04 tdo 81 b8 96 swo e e p05 traced0 tioa5_2 sin4_2 82 c8 97 int00_1 e f - d8 - vss - 20 fujitsu semiconductor confidential r2.0 ds706-00007-1v0-e mb9b100 series pin no. lqfp-100 bga-112 lqfp-120 pin name i/o circuit type pin state type p06 traced1 tiob5_2 sot4_2 (sda4_2) 83 d9 98 int01_1 e f p07 traced2 adtg_0 84 a7 99 sck4_2 (scl4_2) e g p08 traced3 tioa0_2 85 b7 100 cts4_2 e g p09 traceclk tiob0_2 86 c7 101 rts4_2 e g p0a sin4_0 int00_2 frck1_0 87 d7 102 mad07 e h p0b sot4_0 (sda4_0) tiob6_1 ic10_0 88 a6 103 mad06 e i p0c sck4_0 (scl4_0) tioa6_1 ic11_0 89 b6 104 mad05 e i p0d rts4_0 tioa3_2 ic12_0 90 c6 105 mad04 e i 21 fujitsu semiconductor confidential r2.0 ds706-00007-1v0-e mb9b100 series pin no. lqfp-100 bga-112 lqfp-120 pin name i/o circuit type pin state type p0e cts4_0 tiob3_2 ic13_0 91 a5 106 mad03 e i - d4 - vss - - c3 - vss - p0f nmix 92 b5 107 mad02 e j p68 sck3_0 (scl3_0) tiob7_2 - - 108 int12_2 e h p67 sot3_0 (sda3_0) - - 109 tioa7_2 e i p66 sin3_0 adtg_8 - - 110 int11_2 e h p65 tiob7_0 - - 111 sck5_1 (scl5_1) e i p64 tioa7_0 sot5_1 (sda5_1) - - 112 int10_2 e h p63 int03_0 sin5_1 93 d6 113 mad01 e h p62 sck5_0 (scl5_0) adtg_3 94 c5 114 mad00 e i p61 sot5_0 (sda5_0) 95 b4 115 tiob2_2 e i 22 fujitsu semiconductor confidential r2.0 ds706-00007-1v0-e 23 fujitsu semiconductor confidential r2.0 mb9b100 series pin no. lqfp-100 bga-112 lqfp-120 pin name i/o circuit type pin state type p60 sin5_0 tioa2_2 96 c4 116 int15_1 e h 97 a4 117 vcc - 98 a3 118 p80 h o 99 a2 119 p81 h o 100 a1 120 vss - ds706-00007-1v0-e mb9b100 series ? signal description the number after the underscore ("_") in pin name s such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin. pin no. module pin name function lqfp- 100 bga- 112 lqfp- 120 adtg_0 84 a7 99 adtg_1 7 d3 7 adtg_2 18 f4 23 adtg_3 94 c5 114 adtg_4 - - 81 adtg_5 70 d11 80 adtg_6 12 e4 17 adtg_7 30 j5 35 adtg_8 a/d converter external trigger input pin. - - 110 an00 52 j11 62 an01 53 j10 63 an02 54 j8 64 an03 55 h10 65 an04 56 h9 66 an05 57 h7 67 an06 58 g10 68 an07 59 g9 69 an08 63 g8 73 an09 64 f10 74 an10 65 f9 75 an11 66 e11 76 an12 67 e10 77 an13 68 f8 78 an14 69 e9 79 adc an15 a/d converter analog input pin. anxx describes adc ch.xx. 70 d11 80 tioa0_0 27 j4 32 tioa0_1 19 g3 24 tioa0_2 base timer ch.0 tioa pin. 85 b7 100 tiob0_0 40 j6 45 tiob0_1 9 e1 14 base timer 0 tiob0_2 base timer ch.0 tiob pin. 86 c7 101 tioa1_0 28 l5 33 tioa1_1 20 h1 25 tioa1_2 base timer ch.1 tioa pin. 5 d1 5 tiob1_0 41 l7 46 tiob1_1 10 e2 15 base timer 1 tiob1_2 base timer ch.1 tiob pin. 6 d2 6 tioa2_0 29 k5 34 tioa2_1 21 h2 26 tioa2_2 base timer ch.2 tioa pin. 96 c4 116 tiob2_0 42 k7 47 tiob2_1 11 e3 16 base timer 2 tiob2_2 base timer ch.2 tiob pin. 95 b4 115 24 fujitsu semiconductor confidential r2.0 ds706-00007-1v0-e mb9b100 series the number after the underscore ("_") in pin name s such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin. pin no. module pin name function lqfp- 100 bga- 112 lqfp- 120 tioa3_0 30 j5 35 tioa3_1 22 g4 27 tioa3_2 base timer ch.3 tioa pin. 90 c6 105 tiob3_0 43 h6 48 tiob3_1 12 e4 17 base timer 3 tiob3_2 base timer ch.3 tiob pin. 91 a5 106 tioa4_0 31 h5 36 tioa4_1 23 h3 28 tioa4_2 base timer ch.4 tioa pin. - - 51 tiob4_0 44 j7 49 tiob4_1 13 f1 18 base timer 4 tiob4_2 base timer ch.4 tiob pin. - - 52 tioa5_0 32 l6 37 tioa5_1 24 j2 29 tioa5_2 base timer ch.5 tioa pin. 82 c8 97 tiob5_0 45 k8 50 tiob5_1 14 f2 19 base timer 5 tiob5_2 base timer ch.5 tiob pin. 83 d9 98 tioa6_1 base timer ch.6 tioa pin. 89 b6 104 base timer 6 tiob6_1 base timer ch.6 tiob pin. 88 a6 103 tioa7_0 - - 112 tioa7_1 71 d10 86 tioa7_2 base timer ch.7 tioa pin. - - 109 tiob7_0 - - 111 tiob7_1 72 e8 87 base timer 7 tiob7_2 base timer ch.7 tiob pin. - - 108 25 fujitsu semiconductor confidential r2.0 ds706-00007-1v0-e mb9b100 series the number after the underscore ("_") in pin name s such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin. pin no. module pin name function lqfp- 100 bga- 112 lqfp- 120 swclk serial wire debug interface clock input. 78 b9 93 swdio serial wire debug interf ace data input / output. 80 a8 95 swo serial wire viewer output. 81 b8 96 tck j-tag test clock input. 78 b9 93 tdi j-tag test data input. 79 b11 94 tdo j-tag debug data output. 81 b8 96 tms j-tag test mode state input/output. 80 a8 95 traceclk trace clk output of etm. 86 c7 101 traced0 82 c8 97 traced1 83 d9 98 traced2 84 a7 99 traced3 trace data output of etm. 85 b7 100 debugger trstx j-tag test reset input. 77 a9 92 mad00 94 c5 114 mad01 93 d6 113 mad02 92 b5 107 mad03 91 a5 106 mad04 90 c6 105 mad05 89 b6 104 mad06 88 a6 103 mad07 87 d7 102 mad08 55 h10 65 mad09 54 j8 64 mad10 45 k8 50 mad11 44 j7 49 mad12 43 h6 48 mad13 42 k7 47 mad14 41 l7 46 mad15 40 j6 45 mad16 39 k6 44 mad17 32 l6 37 mad18 31 h5 36 mad19 30 j5 35 mad20 29 k5 34 mad21 28 l5 33 mad22 27 j4 32 mad23 14 f2 19 mad24 external bus inte rface address bus. 13 f1 18 mcsx0 57 h7 67 mcsx1 56 h9 66 mcsx2 16 g1 21 mcsx3 15 f3 20 mcsx4 - - 83 mcsx5 - - 82 mcsx6 - - 81 external bus mcsx7 external bus interface chip select output pin. 8 d5 8 26 fujitsu semiconductor confidential r2.0 ds706-00007-1v0-e mb9b100 series the number after the underscore ("_") in pin name s such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin. pin no. module pin name function lqfp- 100 bga- 112 lqfp- 120 mdata0 2 c1 2 mdata1 3 c2 3 mdata2 4 b3 4 mdata3 5 d1 5 mdata4 6 d2 6 mdata5 7 d3 7 mdata6 9 e1 14 mdata7 10 e2 15 mdata8 63 g8 73 mdata9 64 f10 74 mdata10 65 f9 75 mdata11 66 e11 76 mdata12 67 e10 77 mdata13 68 f8 78 mdata14 69 e9 79 mdata15 external bus interface data bus. 70 d11 80 mdqm0 11 e3 16 mdqm1 external bus interface byte mask signal output. 12 e4 17 mnale external bus interface ale signal to control nand flash output pin. - - 9 mncle external bus interface cle signal to control nand flash output pin. - - 10 mnrex external bus interface read enable signal to control nand flash. - - 12 mnwex external bus interface write enable signal to control nand flash. - - 11 moex external bus inte rface read enable sign al for sram. 58 g10 68 external bus mwex external bus interface write enable signal for sram. 59 g9 69 27 fujitsu semiconductor confidential r2.0 ds706-00007-1v0-e mb9b100 series the number after the underscore ("_") in pin name s such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin. pin no. module pin name function lqfp- 100 bga- 112 lqfp- 120 int00_0 2 c1 2 int00_1 82 c8 97 int00_2 external interrupt request 00 input pin. 87 d7 102 int01_0 3 c2 3 int01_1 83 d9 98 int01_2 external interrupt request 01 input pin. - - 85 int02_0 4 b3 4 int02_1 53 j10 63 int02_2 external interrupt request 02 input pin. - - 82 int03_0 93 d6 113 int03_1 56 h9 66 int03_2 external interrupt request 03 input pin. 9 e1 14 int04_0 12 e4 17 int04_1 59 g9 69 int04_2 external interrupt request 04 input pin. 10 e2 15 int05_0 74 c10 89 int05_1 65 f9 75 int05_2 external interrupt request 05 input pin. 11 e3 16 int06_1 73 c11 88 int06_2 external interrupt request 06 input pin. 45 k8 50 int07_2 external interrupt request 07 input pin. 5 d1 5 int08_1 14 f2 19 int08_2 external interrupt request 08 input pin. 8 d5 8 int09_1 15 f3 20 int09_2 external interrupt request 09 input pin. - - 11 int10_1 16 g1 21 int10_2 external interrupt request 10 input pin. - - 112 int11_1 17 g2 22 int11_2 external interrupt request 11 input pin. - - 110 int12_1 27 j4 32 int12_2 external interrupt request 12 input pin. - - 108 int13_1 28 l5 33 int13_2 external interrupt request 13 input pin. - - 52 int14_1 39 k6 44 int14_2 external interrupt request 14 input pin. - - 53 int15_1 96 c4 116 int15_2 external interrupt request 15 input pin. - - 54 external interrupt nmix non-maskable interrupt input. 92 b5 107 28 fujitsu semiconductor confidential r2.0 ds706-00007-1v0-e mb9b100 series the number after the underscore ("_") in pin name s such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin. pin no. module pin name function lqfp- 100 bga- 112 lqfp- 120 p00 77 a9 92 p01 78 b9 93 p02 79 b11 94 p03 80 a8 95 p04 81 b8 96 p05 82 c8 97 p06 83 d9 98 p07 84 a7 99 p08 85 b7 100 p09 86 c7 101 p0a 87 d7 102 p0b 88 a6 103 p0c 89 b6 104 p0d 90 c6 105 p0e 91 a5 106 p0f general-purpose i/o port 0. 92 b5 107 p10 52 j11 62 p11 53 j10 63 p12 54 j8 64 p13 55 h10 65 p14 56 h9 66 p15 57 h7 67 p16 58 g10 68 p17 59 g9 69 p18 63 g8 73 p19 64 f10 74 p1a 65 f9 75 p1b 66 e11 76 p1c 67 e10 77 p1d 68 f8 78 p1e 69 e9 79 p1f general-purpose i/o port 1. 70 d11 80 p20 74 c10 89 p21 73 c11 88 p22 72 e8 87 p23 71 d10 86 p24 - - 85 p25 - - 84 p26 - - 83 p27 - - 82 gpio p28 general-purpose i/o port 2. - - 81 29 fujitsu semiconductor confidential r2.0 ds706-00007-1v0-e mb9b100 series 30 fujitsu semiconductor confidential r2.0 the number after the underscore ("_") in pin name s such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin. pin no. module pin name function lqfp- 100 bga- 112 lqfp- 120 p30 9 e1 14 p31 10 e2 15 p32 11 e3 16 p33 12 e4 17 p34 13 f1 18 p35 14 f2 19 p36 15 f3 20 p37 16 g1 21 p38 17 g2 22 p39 18 f4 23 p3a 19 g3 24 p3b 20 h1 25 p3c 21 h2 26 p3d 22 g4 27 p3e 23 h3 28 p3f general-purpose i/o port 3. 24 j2 29 p40 27 j4 32 p41 28 l5 33 p42 29 k5 34 p43 30 j5 35 p44 31 h5 36 p45 32 l6 37 p46 36 l3 41 p47 37 k3 42 p48 39 k6 44 p49 40 j6 45 p4a 41 l7 46 p4b 42 k7 47 p4c 43 h6 48 p4d 44 j7 49 p4e general-purpose i/o port 4. 45 k8 50 p50 2 c1 2 p51 3 c2 3 p52 4 b3 4 p53 5 d1 5 p54 6 d2 6 p55 7 d3 7 p56 8 d5 8 p57 - - 9 p58 - - 10 p59 - - 11 p5a - - 12 gpio p5b general-purpose i/o port 5. - - 13 ds706-00007-1v0-e mb9b100 series the number after the underscore ("_") in pin name s such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin. pin no. module pin name function lqfp- 100 bga- 112 lqfp- 120 p60 96 c4 116 p61 95 b4 115 p62 94 c5 114 p63 93 d6 113 p64 - - 112 p65 - - 111 p66 - - 110 p67 - - 109 p68 general-purpose i/o port 6. - - 108 p70 - - 51 p71 - - 52 p72 - - 53 p73 - - 54 p74 general-purpose i/o port 7. - - 55 p80 98 a3 118 gpio p81 general-purpose i/o port 8. 99 a2 119 sin0_0 73 c11 88 sin0_1 multifunction serial interface ch.0 input pin. 56 h9 66 sot0_0 (sda0_0) 72 e8 87 sot0_1 (sda0_1) multifunction serial interface ch.0 output pin. this pin operates as sot0 when it is used in a uart/csio (operation modes 0 to 2) and as sda0 when it is used in an i 2 c (operation mode 4). 57 h7 67 sck0_0 (scl0_0) 71 d10 86 multi function serial 0 sck0_1 (scl0_1) multifunction serial interface ch.0 clock i/o pin. this pin operates as sck0 when it is used in a uart/csio (operation modes 0 to 2) and as scl0 when it is used in an i 2 c (operation mode 4). 58 g10 68 sin1_0 - - 8 sin1_1 multifunction serial interface ch.1 input pin. 53 j10 63 sot1_0 (sda1_0) - - 9 sot1_1 (sda1_1) multifunction serial interface ch.1 output pin. this pin operates as sot1 when it is used in a uart/csio (operation modes 0 to 2) and as sda1 when it is used in an i 2 c (operation mode 4). 54 j8 64 sck1_0 (scl1_0) - - 10 multi function serial 1 sck1_1 (scl1_1) multifunction serial interface ch.1 clock i/o pin. this pin operates as sck1 when it is used in a uart/csio (operation modes 0 to 2) and as scl1 when it is used in an i 2 c (operation mode 4). 55 h10 65 31 fujitsu semiconductor confidential r2.0 ds706-00007-1v0-e mb9b100 series the number after the underscore ("_") in pin name s such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin. pin no. module pin name function lqfp- 100 bga- 112 lqfp- 120 sin2_0 - - 53 sin2_1 - - 85 sin2_2 multifunction serial interface ch.2 input pin. 59 g9 69 sot2_0 (sda2_0) - - 54 sot2_1 (sda2_1) - - 84 sot2_2 (sda2_2) multifunction serial interface ch.2 output pin. this pin operates as sot2 when it is used in a uart/csio (operation modes 0 to 2) and as sda2 when it is used in an i 2 c (operation mode 4). 63 g8 73 sck2_0 (scl2_0) - - 55 sck2_1 (scl2_1) - - 83 multi function serial 2 sck2_2 (scl2_2) multifunction serial interface ch.2 clock i/o pin. this pin operates as sck2 when it is used in a uart/csio (operation modes 0 to 2) and as scl2 when it is used in an i 2 c (operation mode 4). 64 f10 74 sin3_0 - - 110 sin3_1 2 c1 2 sin3_2 multifunction serial interface ch.3 input pin. 39 k6 44 sot3_0 (sda3_0) - - 109 sot3_1 (sda3_1) 3 c2 3 sot3_2 (sda3_2) multifunction serial interface ch.3 output pin. this pin operates as sot3 when it is used in a uart/csio (operation modes 0 to 2) and as sda3 when it is used in an i 2 c (operation mode 4). 40 j6 45 sck3_0 (scl3_0) - - 108 sck3_1 (scl3_1) 4 b3 4 multi function serial 3 sck3_2 (scl3_2) multifunction serial interface ch.3 clock i/o pin. this pin operates as sck3 when it is used in a uart/csio (operation modes 0 to 2) and as scl3 when it is used in an i 2 c (operation mode 4). 41 l7 46 32 fujitsu semiconductor confidential r2.0 ds706-00007-1v0-e mb9b100 series the number after the underscore ("_") in pin name s such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin. pin no. module pin name function lqfp- 100 bga- 112 lqfp- 120 sin4_0 87 d7 102 sin4_1 65 f9 75 sin4_2 multifunction serial interface ch.4 input pin. 82 c8 97 sot4_0 (sda4_0) 88 a6 103 sot4_1 (sda4_1) 66 e11 76 sot4_2 (sda4_2) multifunction serial interface ch.4 output pin. this pin operates as sot4 when it is used in a uart/csio (operation modes 0 to 2) and as sda4 when it is used in an i 2 c (operation mode 4). 83 d9 98 sck4_0 (scl4_0) 89 b6 104 sck4_1 (scl4_1) 67 e10 77 sck4_2 (scl4_2) multifunction serial interface ch.4 clock i/o pin. this pin operates as sck4 when it is used in a uart/csio (operation modes 0 to 2) and as scl4 when it is used in an i 2 c (operation mode 4). 84 a7 99 rts4_0 90 c6 105 rts4_1 69 e9 79 rts4_2 multifunction serial interface ch.4 rts output pin. 86 c7 101 cts4_0 91 a5 106 cts4_1 68 f8 78 multi function serial 4 cts4_2 multifunction serial interface ch.4 cts input pin. 85 b7 100 sin5_0 96 c4 116 sin5_1 93 d6 113 sin5_2 multifunction serial interface ch.5 input pin. 15 f3 20 sot5_0 (sda5_0) 95 b4 115 sot5_1 (sda5_1) - - 112 sot5_2 (sda5_2) multifunction serial interface ch.5 output pin. this pin operates as sot5 when it is used in a uart/csio (operation modes 0 to 2) and as sda5 when it is used in an i 2 c (operation mode 4). 16 g1 21 sck5_0 (scl5_0) 94 c5 114 sck5_1 (scl5_1) - - 111 multi function serial 5 sck5_2 (scl5_2) multifunction serial interface ch.5 clock i/o pin. this pin operates as sck5 when it is used in a uart/csio (operation modes 0 to 2) and as scl5 when it is used in an i 2 c (operation mode 4). 17 g2 22 33 fujitsu semiconductor confidential r2.0 ds706-00007-1v0-e mb9b100 series the number after the underscore ("_") in pin name s such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin. pin no. module pin name function lqfp- 100 bga- 112 lqfp- 120 sin6_0 5 d1 5 sin6_1 multifunction serial interface ch.6 input pin. 12 e4 17 sot6_0 (sda6_0) 6 d2 6 sot6_1 (sda6_1) multifunction serial interface ch.6 output pin. this pin operates as sot6 when it is used in a uart/csio (operation modes 0 to 2) and as sda6 when it is used in an i 2 c (operation mode 4). 11 e3 16 sck6_0 (scl6_0) 7 d3 7 multi function serial 6 sck6_1 (scl6_1) multifunction serial interface ch.6 clock i/o pin. this pin operates as sck6 when it is used in a uart/csio (operation modes 0 to 2) and as scl6 when it is used in an i 2 c (operation mode 4). 10 e2 15 sin7_0 - - 11 sin7_1 multifunction serial interface ch.7 input pin. 45 k8 50 sot7_0 (sda7_0) - - 12 sot7_1 (sda7_1) multifunction serial interface ch.7 output pin. this pin operates as sot7 when it is used in a uart/csio (operation modes 0 to 2) and as sda7 when it is used in an i 2 c (operation mode 4). 44 j7 49 sck7_0 (scl7_0) - - 13 multi function serial 7 sck7_1 (scl7_1) multifunction serial interface ch.7 clock i/o pin. this pin operates as sck7 when it is used in a uart/csio (operation modes 0 to 2) and as scl7 when it is used in an i 2 c (operation mode 4). 43 h6 48 34 fujitsu semiconductor confidential r2.0 ds706-00007-1v0-e mb9b100 series the number after the underscore ("_") in pin name s such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin. pin no. module pin name function lqfp- 100 bga- 112 lqfp- 120 dtti0x_0 18 f4 23 dtti0x_1 input signal controlling wave form generator outputs rto00 to rto05 of multi-function timer 0. 69 e9 79 frck0_0 13 f1 18 frck0_1 16-bit free-run timer ch.0 external clock input pin. 70 d11 80 ic00_0 17 g2 22 ic00_1 65 f9 75 ic01_0 16 g1 21 ic01_1 66 e11 76 ic02_0 15 f3 20 ic02_1 67 e10 77 ic03_0 14 f2 19 ic03_1 16-bit input capture ch.0 input pin of multi-function timer 0. icxx desicribes chanel number. 68 f8 78 rto00_0 (ppg00_0) 19 g3 24 rto00_1 (ppg00_1) wave form generator output of multi-function timer 0. this pin operates as ppg00 when it is used in ppg 0 output modes. 71 d10 86 rto01_0 (ppg00_0) 20 h1 25 rto01_1 (ppg00_1) wave form generator output of multi-function timer 0. this pin operates as ppg00 when it is used in ppg 0 output modes. - - 85 rto02_0 (ppg02_0) 21 h2 26 rto02_1 (ppg02_1) wave form generator output of multi-function timer 0. this pin operates as ppg02 when it is used in ppg 0 output modes. - - 84 rto03_0 (ppg02_0) 22 g4 27 rto03_1 (ppg02_1) wave form generator output of multi-function timer 0. this pin operates as ppg02 when it is used in ppg 0 output modes. - - 83 rto04_0 (ppg04_0) 23 h3 28 rto04_1 (ppg04_1) wave form generator output of multi-function timer 0. this pin operates as ppg04 when it is used in ppg 0 output modes. - - 82 rto05_0 (ppg04_0) 24 j2 29 multi function timer 0 rto05_1 (ppg04_1) wave form generator output of multi-function timer 0. this pin operates as ppg04 when it is used in ppg 0 output modes. - - 81 35 fujitsu semiconductor confidential r2.0 ds706-00007-1v0-e mb9b100 series the number after the underscore ("_") in pin name s such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin. pin no. module pin name function lqfp- 100 bga- 112 lqfp- 120 dtti1x_0 8 d5 8 dtti1x_1 input signal controlling wave form generator outputs rto10 to rto15 of multi-function timer 1. 39 k6 44 frck1_0 87 d7 102 frck1_1 16-bit free-run timer ch.1 external clock input pin. 44 j7 49 ic10_0 88 a6 103 ic10_1 40 j6 45 ic11_0 89 b6 104 ic11_1 41 l7 46 ic12_0 90 c6 105 ic12_1 42 k7 47 ic13_0 91 a5 106 ic13_1 16-bit input capture ch.0 input pin of multi-function timer 1. icxx desicribes chanel number. 43 h6 48 rto10_0 (ppg10_0) 2 c1 2 rto10_1 (ppg10_1) wave form generator output of multi-function timer 1. this pin operates as ppg10 when it is used in ppg 1 output modes. 27 j4 32 rto11_0 (ppg10_0) 3 c2 3 rto11_1 (ppg10_1) wave form generator output of multi-function timer 1. this pin operates as ppg10 when it is used in ppg 1 output modes. 28 l5 33 rto12_0 (ppg12_0) 4 b3 4 rto12_1 (ppg12_1) wave form generator output of multi-function timer 1. this pin operates as ppg12 when it is used in ppg 1 output modes. 29 k5 34 rto13_0 (ppg12_0) 5 d1 5 rto13_1 (ppg12_1) wave form generator output of multi-function timer 1. this pin operates as ppg12 when it is used in ppg 1 output modes. 30 j5 35 rto14_0 (ppg14_0) 6 d2 6 rto14_1 (ppg14_1) wave form generator output of multi-function timer 1. this pin operates as ppg14 when it is used in ppg 1 output modes. 31 h5 36 rto15_0 (ppg14_0) 7 d3 7 multi function timer 1 rto15_1 (ppg14_1) wave form generator output of multi-function timer 1. this pin operates as ppg14 when it is used in ppg 1 output modes. 32 l6 37 36 fujitsu semiconductor confidential r2.0 ds706-00007-1v0-e mb9b100 series the number after the underscore ("_") in pin name s such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin. pin no. module pin name function lqfp- 100 bga- 112 lqfp- 120 ain0_0 9 e1 14 ain0_1 40 j6 45 ain0_2 qprc ch.0 ain input pin. 2 c1 2 bin0_0 10 e2 15 bin0_1 41 l7 46 bin0_2 qprc ch.0 bin input pin. 3 c2 3 zin0_0 11 e3 16 zin0_1 42 k7 47 quadrature position/ revolution counter 0 zin0_2 qprc ch.0 zin input pin. 4 b3 4 ain1_1 74 c10 89 ain1_2 qprc ch.1 ain input pin. 43 h6 48 bin1_1 73 c11 88 bin1_2 qprc ch.1 bin input pin. 44 j7 49 zin1_1 72 e8 87 quadrature position/ revolution counter 1 zin1_2 qprc ch.1 zin input pin. 45 k8 50 37 fujitsu semiconductor confidential r2.0 ds706-00007-1v0-e 38 fujitsu semiconductor confidential r2.0 mb9b100 series the number after the underscore ("_") in pin name s such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin. pin no. module pin name function lqfp- 100 bga- 112 lqfp- 120 reset initx external reset input. a re set is valid when initx=l. 38 k4 43 md0 mode 0 pin. during normal operation, md0=l must be input. during serial programming to flash memory, md0=h must be input. 47 l8 57 mode md1 mode 1 pin. input must always be at the "l" level. 46 k9 56 vcc power pin. 1 b1 1 vcc power pin. 26 j1 31 vcc power pin. 35 k1 40 vcc power pin. 51 k11 61 vcc power pin. 76 a10 91 power vcc power pin. 97 a4 117 vss gnd pin. - b2 - vss gnd pin. 25 l1 30 vss gnd pin. - k2 - vss gnd pin. - j3 - vss gnd pin. - h4 - vss gnd pin. 34 l4 39 vss gnd pin. 50 l11 60 vss gnd pin. - k10 - vss gnd pin. - j9 - vss gnd pin. - h8 - vss gnd pin. - b10 - vss gnd pin. - c9 - vss gnd pin. 75 a11 90 vss gnd pin. - d8 - vss gnd pin. - d4 - vss gnd pin. - c3 - gnd vss gnd pin. 100 a1 120 x0 main clock (oscillation) input pin. 48 l9 58 x0a sub clock (oscillation) input pin. 36 l3 41 x1 main clock (oscillation) i/o pin. 49 l10 59 x1a sub clock (oscillation) i/o pin. 37 k3 42 clock crout internal cr-osc clock output port. 74 c10 89 avcc a/d converter analog power pin. 60 h11 70 adc power avrh a/d converter analog reference voltage input pin. 61 f11 71 adc gnd avss a/d converter gnd pin. 62 g11 72 c-pin c power stabilization capacity pin. 33 l2 38 ds706-00007-1v0-e mb9b100 series ? i/o circuit type type circuit remarks a ? oscillation feedback resistor : approximately 1m ? ? with standby mode control b x1 ? cmos level hysteresis in put ? pull-up resistor : approximately 50k ? c mode input control pin ? cmos level input ? with high-voltage control for flash memory test pull-up resistor cmos level hysteresis input clock input x0 standby mode control 39 fujitsu semiconductor confidential r2.0 ds706-00007-1v0-e mb9b100 series 40 fujitsu semiconductor confidential r2.0 type circuit remarks d ? it is possible to select the low speed oscillation / gpio function. when the low speed oscillation is selected. ? oscillation feedback resistor : approximately 20m ? ? with standby mode control w hen the gpio is selected. ? cmos level output. ? cmos level hysteresis input ? with pull-up resistor control ? with standby mode control ? pull-up resistor : approximately 50k ? ? ioh=-4ma, iol=4ma standby mode control standby mode control digital output digital output standby mode control x0a clock input digital input p-ch n-ch digital input digital output digital output p-ch n-ch x1a r r p-ch pull-up resistor control p-ch pull-up resistor control ds706-00007-1v0-e mb9b100 series 41 fujitsu semiconductor confidential r2.0 type circuit remarks e ? cmos level output ? cmos level hysteresis input ? with pull-up resistor control ? with standby mode control ? pull-up resistor : approximately 50k ? ? ioh=-4ma, iol=4ma f ? cmos level output ? cmos level hysteresis input ? with input control ? analog input ? with pull-up resistor control ? with standby mode control ? pull-up resistor : approximately 50k ? ? ioh=-4ma, iol=4ma standby mode control digital output pull-up resistor control digital output digital input p-ch p-ch n-ch digital output digital output pull-up resistor control input control standby mode control a nalog input digital input p-ch p-ch n-ch ds706-00007-1v0-e 42 mb9b100 series remarks type circuit g fujitsu semiconductor confidential r2.0 ? cmos leve l output ? cmos level hysteresis input ? with pull-up resistor control ? with standby mode control ? pull-up resistor : approximately 50k ? ? ioh=-12ma, iol=12ma h ? cmos level output ? cmos level hysteresis input ? with standby mode control standby mode control digital output pull-up resistor control digital output digital input p-ch p-ch n-ch p-ch digital output n-ch digital output digital input standby mode control ds706-00007-1v0-e mb9b100 series ? precautions for handling the devices any semiconductor devices have inherently a certain rate of failure. the possibility of failure is greatly affected by the conditions in which they are used (c ircuit conditions, environmental conditions, etc.). this page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your fujitsu semiconductor devices. ? precautions for product design this section describes precautions when designing electronic equipment usi ng semiconductor devices. ? absolute maximum ratings semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. ? recommended operating conditions the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the device?s electri cal characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating co ndition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. ? processing and protection of pins these precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. 1. preventing over-voltage and over-current conditions exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cas es leads to permanent damage of the device. try to prevent such overvoltage or over-current conditions at the design stage. 2. protection of output pins shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. such conditions if present for extended periods of time can damage the device. therefore, avoid this type of connection. 3. handling of unused input pins unconnected input pins with very high impedance levels can adversely affect stability of operation. such pins should be connected through an appropriate resistance to a power supply pin or ground pin. ? latch-up semiconductor devices are constructed by the formation of p-type and n-type areas on a substrate. when subjected to abnormally high voltages, inte rnal parasitic pnpn junctions (called thyristor structures) may be formed, causing large current le vels in excess of several hundred ma to flow continuously at the power supply pin. this condition is called latch-up. note: the occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. to prevent this from happening, do the following: (a) be sure that voltages applied to pins do not exceed the absolute maximum ratings. this should include attention to abnormal noise, surge levels, etc. (b) be sure that abnormal current flows do not occur during the power-on sequence. 43 fujitsu semiconductor confidential r2.0 ds706-00007-1v0-e mb9b100 series ? observance of safety regulations and standards most countries in the world have established standa rds and regulations regarding safety, protection from electromagnetic interference, etc. customers are re quested to observe applicable regulations and standards in the design of products. ? fail-safe design any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorpora ting safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. ? precautions related to usage of devices fujitsu semiconductor devices are intended for us e in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our pro ducts in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requ ested to consult with fujitsu sales representatives before such use. the co mpany will not be responsible for damages arising from such use without prior approval. 44 fujitsu semiconductor confidential r2.0 ds706-00007-1v0-e mb9b100 series ? precautions for package mounting package mounting may be either lead insertion type or surface mount type. in either case, for heat resistance during soldering, you should only mount under fujitsu's recommended conditions. for detailed information about mount conditions, contact your fujitsu sales representative. ? lead insertion type mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. in this case, the soldering process usually causes lead s to be subjected to thermal stress in excess of the absolute ratings for storage temperature. mounting processes should conform to fujitsu recommended mounting conditions. if socket mounting is used, differences in surface treat ment of the socket contacts and ic lead surfaces can lead to contact deterioration after long period s. for this reason it is recommended that the surface treatment of socket contacts and ic leads be verified before mounting. ? surface mount type surface mount packaging has longer an d thinner leads than lead-insertio n packaging, and therefore leads are more easily deformed or bent. the use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. you must use appropriate mounting techniques. fujitsu recommends the solder reflow method, and has established a ranking of mounting conditions for each product. users are advised to mount packages in accordance with fujitsu ranking of recommended conditions. ? lead-free packaging note: when ball grid array (bga) packages with sn-ag-cu balls are mounted using sn-pb eutectic soldering, junction strength may be reduced under some conditions of use. ? storage of semiconductor devices because plastic chip packages are formed from pl astic resins, exposure to natural environmental conditions will cause ab sorption of moisture. during mounting, th e application of heat to a package that has absorbed moisture can cause surfaces to peel, re ducing moisture resistance and causing packages to crack. to prevent, do the following: ? avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. store products in locations where temperature changes are slight. ? use dry boxes for product storage. products should be stored below 70% relative humidity, and at temperatures between 5 ? c and 30 ? c when you open dry package that recommends humidity 40% to 70% relative humidity. ? when necessary, fujitsu packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. devices sh ould be sealed in their aluminum laminate bags for storage. ? avoid storing packages where they are exposed to corrosive gases or high levels of dust. ? baking packages that have absorbed moisture may be de-moisturized by baking (heat drying). follow the fujitsu recommended conditions for baking. condition:+125 ? c/24 h 45 fujitsu semiconductor confidential r2.0 ds706-00007-1v0-e mb9b100 series ? static electricity because semiconductor devices are particularly suscep tible to damage by static electricity, you must take the following precautions: ? maintain relative humidity in the working environment between 40% and 70%. use of an apparatus for ion generation may be needed to remove electricity. ? electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. ? eliminate static body elect ricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 m ? ). wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. ? ground all fixtures and instruments, or protect with anti-static measures. ? avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies. ? precautions for use environment reliability of semiconductor devices depends on ambient temperature and other conditions as described above. for reliable performance, do the following: 1. humidity prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. if high humidity levels are anticipated, consider anti-humidity processing. 2. discharge of static electricity when high-voltage charges exist close to semic onductor devices, discharges can cause abnormal operation. in such cases, use anti-static measures or processing to prevent discharges. 3. corrosive gases, dust, or oil exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. if you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. 4. radiation, including cosmic radiation most devices are not designed for environments involving exposure to radiation or cosmic radiation. users should provide shie lding as appropriate. 5. smoke, flame note: plastic molded devices are flammable, and therefore should not be used near combustible substances. if devices begin to smoke or burn, there is danger of the release of toxic gases. customers considering the use of fujitsu products in other special environmental conditions should consult with fujitsu sales representatives. please check the latest handling precautions at the following url. http://edevice.fujitsu.com/fj/handling-e.pdf 46 fujitsu semiconductor confidential r2.0 ds706-00007-1v0-e mb9b100 series ? handling devices ? power supply pins in products with multiple vcc and vss pins, respectiv e pins at the same potential are interconnected within the device in order to prevent malfunctions such as latch-up. however, all of these pins should be connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. moreover, connect the current supply source with the vcc and vss pins of this device at low impedance. it is also advisable that a cerami c capacitor of approximately 0.1 f be connected as a bypass capacitor between vcc and vss near this device. ? crystal oscillator circuit noise near the x0/x1 and x0a/x1a pins may cause the device to malfunction. design the printed circuit board so that x0/x1, x0a/x1a pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as clos e to the device as possible. it is strongly recommended that the pc board artwork be designed such that the x0/x1 and x0a/x1a pins are surrounded by ground plane as this is expected to produce stable operation. ? using an external clock when using an external clock, the clock signal should be input to the x0,x0a pin only and the x1,x1a pin should be kept open. ? example of using an external clock open x1(x1a) x0(x0a) device ? handling when using multi function serial pin as i 2 c pin if it is using multi function serial pin as i 2 c pins, p-ch transistor of digital output is always disable. however, i 2 c pins need to keep the electrical characteristic like other pins and not to connect to external i 2 c bus system with power off. 47 fujitsu semiconductor confidential r2.0 ds706-00007-1v0-e 48 mb9b100 series ? c pin as this series includes an internal regulator, always connect a bypass capacitor of approximately 4.7 f to the c pin for use by the regulator. gnd 4.7 f vss c device ? mode pins (md0, md1) connect the md pin (md0, md1) direc tly to vcc or vss pins. design the printed circuit board such that the pull-up/down resistance stays low, as well as the distance between the mode pins and vcc pins or vss pins is as short as possible and the connection impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the flash memory data. it is because of preventing the device erroneously switching to test mode due to noise. ? notes on power-on turn power on/off in the following order or at the same time. if not using the a/d converter, connect avcc =vcc and avss = vss. turning on : vcc ? avcc ? av r h turning off : avrh ? av c c ? vcc ? serial communication there is a possibility to receive wrong data due to the noise or ot her causes on the serial communication. therefore, design a printed circuit board so as to avoid noise. consider the case of receiving wron g data due to noise, perform error detection such as by applying a checksum of data at the end. if an e rror is detected, restransmit the data. ? differences in features among the products with different memory sizes and between flash products and mask products the electric characteristics including power consump tion, esd, latch-up, no ise characteristics, and oscillation characteristics among the products with di fferent memory sizes and between flash products and mask products are different because chip layout and memory structures are different. if you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics. fujitsu semiconductor confidential r2.0 ds706-00007-1v0-e mb9b100 series ? block diagram flash i/f cortex-m3 core @80mhz(max.) clock reset generator dual-timer watchdog timer (hardware) dmac 8ch on-chip flash 256/384/512 kbyte multi function timer x2 multi serial if 8ch (with fifo ch.4 7) *hw flow control(ch.4) 16-bit freerun timer 3ch 16-bit output compare 6ch 16-bit input capture 4ch waveform generator 3ch a/d activation compare 3ch 16-bit ppg 3ch watch counter 12bit a/d converter gpio csv main osc pll regurator + lvd external interrupt controller 16-pin + nmi power on reset tpiu rom table etm code ram 16/24/32 kbyte swj-dp multi-layer ahb (max.80mhz) ahb-apb bridge : apb1 (max.40mhz) on-chip sram 16/24/32 kbyte ahb-apb bridge: apb0(max.40mhz) i d sys clk rst mb9bf104/105/106 ahb-apb bridge : apb2 ( max.40mhz) base timer 16-bit 8ch /32-bit 4ch mpu nvic watchdog timer (software) security sub. osc cr 4mhz a/d converter x3 12bit a/d converter 12bit a/d converter trstx,tck tdi,tms traced[3:0], traceclk x0 avcc, avss,avrh an[15:0] tioa[7:0] tiob[7:0] ic0[3:0] dtti[1:0]x rto0[5:0] frck[1:0] vcc,vss c tdo x1 x0a x1a sck[7:0] sin[7:0] sot[7:0] int[15:0] nmix p0[f:0], p1[f:0], ? ? px[x:0], initx mode-ctrl irq-monitor pin-function-ctrl md[1:0] cr 100khz regurator + lvd qprc 2ch ain[1:0] bin[1:0] zin[1:0] regurator ctrl crc accelerator ic1[3:0] ahb-ahb bridge adtg[8:0] rts4 cts4 external bus if mad[24:0] mdata[15:0] mcsx[7:0], moex,mwex, mnale, mncle mnwex, mnrex, mdqm[1:0] rto1[5:0] product device mb9bf104 mb9bf105 mb9bf106 on-chip flash 256kbyte 384kbyte 512kbyte code sram 16kbyte 24kbyte 32kbyte on-chip sram 16kbyte 24kbyte 32kbyte 49 fujitsu semiconductor confidential r2.0 ds706-00007-1v0-e mb9b100 series 50 fujitsu semiconductor confidential r2.0 ? memory map ? mb9b100 series memory map(1) flash 0x0000_0000 0x0010_0000 0x2000_0000 0x1ff8_0000 code sram on chip sram 0x2008_0000 reserved 0x2200_0000 reserved 32mbyte bit band alias 0x2400_0000 reserved 0x4000_0000 peripherals 0x4200_0000 0x6000_0000 0xe000_0000 cortex-m3 private peripherals 0xe010_0000 reserved 0xffff_ffff 32mbyte bit band alias reserved 0x4400_0000 external device area 0x41ff_ffff 0x4000_0000 flash i/f 0x4000_1000 reserved 0x4001_0000 clock/reset 0x4001_2000 0x4001_1000 sw wdt hw wdt 0x4001_5000 reserved 0x4001_3000 dual timer 0x4001_6000 reserved 0x4002_0000 peripherals area mft unit0 0x4002_1000 mft unit1 0x4002_2000 reserved ppg 0x4002_4000 0x4002_5000 base timer 0x4002_6000 qprc 0x4002_7000 a/dc 0x4002_8000 reserved 0x4003_0000 exti 0x4003_1000 int-req. read 0x4003_2000 0x4003_3000 0x4003_4000 0x4003_5000 0x4003_6000 0x4003_7000 reserved gpio lvd 0x4003_8000 mfs 0x4003_9000 crc 0x4003_a000 watch counter 0x4003_b000 reserved 0x4004_0000 ext-bus i/f 0x4005_0000 0x4006_0000 0x4006_1000 0x4006_2000 dmac 0x4006_3000 reserved 0x4003_f000 reserved reserved 0x4002_e000 cr trim 0x4002_f000 reserved 0x4006_4000 reserved security/cr trim 0x0010_2000 please refer to the next page for the memory size details. reserved reserved reserved reserved reserved ds706-00007-1v0-e mb9b100 series 51 fujitsu semiconductor confidential r2.0 ? mb9b100 series memory map(2) flash 512kbyte 0x0000_0000 0x2000_0000 0x1fff_8000 code sram 32kbyte on chip sram 32kbyte 0x2008_0000 reserved security 0x0010_0000 0x0008_0000 reserved 0x2000_8000 cr triming 0x0010_1000 0x0010_2000 flash 256kbyte flash 384kbyte reserved on chip sram 16kbyte code sram 16kbyte 0x0000_0000 0x0000_0000 0x1fff_a000 reserved security 0x0010_0000 0x0006_0000 cr triming 0x0010_1000 0x0010_2000 reserved 0x1fff_c000 reserved security 0x0010_0000 0x0004_0000 cr triming reserved 0x2008_0000 reserved 0x2000_4000 0x2000_0000 0x0010_1000 0x0010_2000 on chip sram 24kbyte code sram 24kbyte 0x2000_6000 0x2000_0000 0x2008_0000 reserved mb9bf106n/r mb9bf105n/r mb9bf104n/r ds706-00007-1v0-e 52 mb9b100 series fujitsu semiconductor confidential r2.0 ? peripheral address map start address end address bus peripherals 0x4000_0000 0x4000_0fff flash i/f register 0x4000_1000 0x4000_ffff ahb reserved 0x4001_0000 0x4001_0fff clock/reset control 0x4001_1000 0x4001_1fff hardware watchdog timer 0x4001_2000 0x4001_2fff software watchdog timer 0x4001_3000 0x4001_4fff reserved 0x4001_5000 0x4001_5fff dual-timer 0x4001_6000 0x4001_ffff apb0 reserved 0x4002_0000 0x4002_0fff multi-function timer unit0 0x4002_1000 0x4002_1fff multi-function timer unit1 0x4002_2000 0x4002_3fff reserved 0x4002_4000 0x4002_4fff ppg 0x4002_5000 0x4002_5fff base timer 0x4002_6000 0x4002_6fff quadrature position/revolution counter 0x4002_7000 0x4002_7fff a/d converter 0x4002_8000 0x4002_dfff reserved 0x4002_e000 0x4002_efff internal cr trimming 0x4002_f000 0x4002_ffff apb1 reserved 0x4003_0000 0x4003_0fff external interrupt controller 0x4003_1000 0x4003_1fff interrupt request batch-read function 0x4003_2000 0x4003_2fff reserved 0x4003_3000 0x4003_3fff gpio 0x4003_4000 0x4003_4fff reserved 0x4003_5000 0x4003_5fff low voltage detector 0x4003_6000 0x4003_6fff reserved 0x4003_7000 0x4003_7fff reserved 0x4003_8000 0x4003_8fff multi-function serial interface 0x4003_9000 0x4003_9fff crc 0x4003_a000 0x4003_afff watch counter 0x4003_b000 0x4003_efff reserved 0x4003_f000 0x4003_ffff apb2 external memory interface 0x4004_0000 0x4004_ffff reserved 0x4005_0000 0x4005_ffff reserved 0x4006_0000 0x4006_0fff dmac register 0x4006_1000 0x4006_1fff reserved 0x4006_2000 0x4006_2fff reserved 0x4006_3000 0x4006_3fff reserved 0x4006_4000 0x41ff_ffff ahb reserved ds706-00007-1v0-e mb9b100 series ? pin status in each cpu state the terms used for pin status have the following meanings. ? initx=0 this is the period when the initx pin is the "l" level. ? initx=1 this is the period when the initx pin is the "h" level. ? spl=0 this is the status that standby pin level setting bit (spl) in standby mode control register (stb_ctl) is set to "0". ? spl=1 this is the status that standby pin level setting bit (spl) in standby mode control register (stb_ctl) is set to "1". ? input enabled indicates that the input function can be used. ? internal input fixed at "0" this is the status that the input function cann ot be used. internal input is fixed at "l". ? hi-z indicates that the output drive transistor is di sabled and the pin is pu t in the hi-z state. ? setting disabled indicates that the setting is disabled. ? maintain previous state maintains the state that was immediately prior to entering the current mode. if a built-in peripheral function is operating, the output follows the peripheral function. if the pin is being used as a port, that output is maintained. ? analog input is enabled indicates that the analog input is enabled. ? trace output indicates that the trace function can be used. 53 fujitsu semiconductor confidential r2.0 ds706-00007-1v0-e mb9b100 series ? list of pin status power-on reset or low voltage detection state initx input state device internal reset state run mode or sleep mode state timer mode or sleep mode state power supply unstable power supply stable power supply stable power supply stable - initx=0 initx=1 initx=1 initx=1 pin status type function group - - - - spl=0 spl=1 a main crystal oscillator input pin input enabled input enabled input enabled input enabled input enabled input enabled b main crystal oscillator output pin h output/ internal input fixed at "0"/ or input enabled h output/ internal input fixed at "0" h output/ internal input fixed at "0" maintain previous state/ h output at oscillation stop (*1)/ internal input fixed at "0" maintain previous state/ h output at oscillation stop (*1)/ internal input fixed at "0" maintain previous state/ h output at oscillation stop (*1)/ internal input fixed at "0" c initx input pin pull-up/ input enabled pull-up/ input enabled pull-up/ input enabled pull-up/ input enabled pull-up/ input enabled pull-up/ input enabled d mode input pin input enabled input enabled input enabled input enabled input enabled input enabled jtag selected hi-z pull-up/ input enabled pull-up/ input enabled maintain previous state e gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state output hi-z/ internal input fixed at "0" trace selected trace output external interrupt enabled selected setting disabled setting disabled setting disabled maintain previous state f gpio selected, or other than above resource selected hi-z hi-z/ input enabled hi-z/ input enabled maintain previous state maintain previous state hi-z/ internal input fixed at "0" 54 fujitsu semiconductor confidential r2.0 ds706-00007-1v0-e mb9b100 series power-on reset or low voltage detection state initx input state device internal reset state run mode or sleep mode state timer mode or sleep mode state power supply unstable power supply stable power supply stable power supply stable - initx=0 initx=1 initx=1 initx=1 pin status type function group - - - - spl=0 spl=1 trace selected setting disabled setting disabled setting disabled trace output g gpio selected, or other than above resource selected hi-z hi-z/ input enabled hi-z/ input enabled maintain previous state maintain previous state hi-z/ internal input fixed at "0" external interrupt enabled selected setting disabled setting disabled setting disabled maintain previous state h gpio selected, or other than above resource selected hi-z hi-z/ input enabled hi-z/ input enabled maintain previous state maintain previous state hi-z/ internal input fixed at "0" i gpio selected, resource selected hi-z hi-z/ input enabled hi-z/ input enabled maintain previous state maintain previous state output hi-z/ internal input fixed at "0" nmix selected setting disabled setting disabled setting disabled maintain previous state j gpio selected, or other than above resource selected hi-z hi-z/ input enabled hi-z/ input enabled maintain previous state maintain previous state hi-z/ internal input fixed at "0" 55 fujitsu semiconductor confidential r2.0 ds706-00007-1v0-e mb9b100 series power-on reset or low voltage detection state initx input state device internal reset state run mode or sleep mode state timer mode or sleep mode state power supply unstable power supply stable power supply stable power supply stable - initx=0 initx=1 initx=1 initx=1 pin status type function group - - - - spl=0 spl=1 analog input selected hi-z hi-z/ internal input fixed at "0"/ analog input enabled hi-z/ internal input fixed at "0"/ analog input enabled hi-z/ internal input fixed at "0"/ analog input enabled hi-z/ internal input fixed at "0"/ analog input enabled hi-z/ internal input fixed at "0"/ analog input enabled k gpio selected, or other than above resource selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi-z/ internal input fixed at "0" external interrupt enabled selected setting disabled setting disabled setting disabled maintain previous state maintain previous state maintain previous state analog input selected hi-z hi-z/ internal input fixed at "0"/ analog input enabled hi-z/ internal input fixed at "0"/ analog input enabled hi-z/ internal input fixed at "0"/ analog input enabled hi-z/ internal input fixed at "0"/ analog input enabled hi-z/ internal input fixed at "0"/ analog input enabled l gpio selected, or other than above resource selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi-z/ internal input fixed at "0" gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state output hi-z/ internal input fixed at "0" m sub crystal oscillator input pin input enabled input enabled input enabled input enabled input enabled input enabled 56 fujitsu semiconductor confidential r2.0 ds706-00007-1v0-e 57 fujitsu semiconductor confidential r2.0 mb9b100 series power-on reset or low voltage detection state initx input state device internal reset state run mode or sleep mode state timer mode or sleep mode state power supply unstable power supply stable power supply stable power supply stable - initx=0 initx=1 initx=1 initx=1 pin status type function group - - - - spl=0 spl=1 gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state output hi-z/ internal input fixed at "0" n sub crystal oscillator output pin hi-z/ internal input fixed at "0" hi-z/ internal input fixed at "0" hi-z/ internal input fixed at "0" maintain previous state maintain previous state/ hi-z at oscillation stop (*2)/ internal input fixed at "0" maintain previous state/ hi-z at oscillation stop (*2)/ internal input fixed at "0" o gpio selected hi-z hi-z/ input enabled hi-z/ input enabled maintain previous state maintain previous state output hi-z/ internal input fixed at "0" *1 : oscillation is stopped at sub timer, sub cr timer mode, and stop mode. *2 : oscillation is stopped at stop mode. ds706-00007-1v0-e mb9b100 series ? electrical characteristics this section describes the electrical characteristics of mb9b100 series. ? absolute maximum ratings / r ecommended operating conditions the following tables show the absolute maximum ratings and recommended operating conditions. 1. absolute maximum ratings (vss = avss = 0.0v) rating parameter symbol min max unit remarks power supply voltage*1 vcc vss - 0.5 vss + 6.5 v analog power supply voltage *2 avcc vss - 0.5 vss + 6.5 v analog reference voltage *2 avrh vss - 0.5 vss + 6.5 v input voltage v i vss - 0.5 vcc + 0.5 ( ? 6.5v) v analog pin input voltage v ia vss - 0.5 avcc + 0.5 ( ? 6.5v) v output voltage v o vss - 0.5 vcc + 0.5 ( ? 6.5v) v 10 ma 4ma type "l" level maximum output current *3 i ol - 20 ma 12ma type 4 ma 4ma type "l" level average output current *4 i olav - 12 ma 12ma type "l" level total maximum output current i ol - 100 ma "l" level total average output current *5 i olav - 50 ma - 10 ma 4ma type "h" level maximum output current *3 i oh - - 20 ma 12ma type - 4 ma 4ma type "h" level average output current *4 i ohav - - 12 ma 12ma type "h" level total maximum output current i oh - - 100 ma "h" level total average output current *5 i ohav - - 50 ma power consumption p d - 800 mw storage temperature t stg - 55 + 150 ? c *1 : vcc must not drop below vss - 0.5v. *2 : be careful not to exceed vcc + 0.5 v, for example, when the power is turned on. *3 : the maximum output current is the peak value for a single pin. *4 : the average output is the average current for a single pin over a period of 100 ms. *5 : the total average output current is the averag e current for all pins over a period of 100 ms. mb9b100 series 2. recommended operating conditions (vss = avss = 0.0v) value parameter symbol conditions min max unit remarks power supply voltage vcc - 2.7 5.5 v analog power supply voltage avcc - 2.7 5.5 v avcc = vcc analog reference voltage avrh - avss avcc v when mounted on four-layer pcb - 40 + 85 ? c - 40 + 85 ? c icc ? 100ma operating temperature fpt-120p-m21 fpt-100p-m20 fpt-100p-m23 bga-112p-m04 ta when mounted on double-sided single-layer pcb - 40 + 70 ? c icc > 100ma mb9b100 series ? dc characteristics the following tables show the dc characteristics. 1. current rating (vcc = avcc = 2.7v to 5.5v, vss = avss = 0v ta = - 40 ? c to + 85 ? c) value parameter symbol pin name conditions min typ max unit remarks - 96 118 ma cpu : 80mhz, peripheral : 40mhz, flash 2wait frwtr.rwt = 10 fsyndn.sd = 000 *1 - 76 94 ma cpu : 60mhz, peripheral : 30mhz, flash 0wait frwtr.rwt = 00 fsyndn.sd = 000 *1 - 66 82 ma cpu : 80mhz, peripheral : 40mhz, flash 5wait frwtr.rwt = 10 fsyndn.sd = 011 *1 normal operation (pll) - 52 65 ma cpu : 60mhz, peripheral : 30mhz, flash 3wait frwtr.rwt = 00 fsyndn.sd = 011 *1 normal operation (built-in high-speed cr) - 6.0 9.2 ma cpu/ peripheral : 4mhz *1, *2 flash 0wait frwtr.rwt = 00 fsyndn.sd = 000 normal operation (sub oscillation) - 0.2 2.24 ma cpu/ peripheral : 32khz flash 0wait frwtr.rwt = 00 fsyndn.sd = 000 *1 icc normal operation (built-in low-speed cr) - 0.3 2.36 ma cpu/ peripheral : 100khz flash 0wait frwtr.rwt = 00 fsyndn.sd = 000 *1 sleep operation (pll) - 43 54 ma peripheral : 40mhz *1 sleep operation (built-in high-speed cr) - 3.5 6.2 ma peripheral : 4mhz *1, *2 sleep operation (sub oscillation) - 0.15 2.18 ma peripheral : 32khz *1 power supply current iccs vcc sleep operation (built in low-speed cr) - 0.22 2.27 ma peripheral : 100khz *1 60 fujitsu semiconductor confidential r2.1 ds706-00007-1v0-e mb9b100 series (continued) value parameter symbol pin name conditions min typ max unit remarks - 50 200 a ta = + 25 ? c, when lvd is off *1 i cch stop mode - - 2 ma ta = + 85 ? c, when lvd is off *1 - 110 300 a ta = + 25 ? c, when lvd is off *1 power supply current i cct timer mode (sub oscillation) - - 2.2 ma ta = + 85 ? c, when lvd is off *1 low voltage detection circuit (lvd) power supply current i cclvd vcc at operation - 2 10 a for occurrence of interrupt *1:when all ports are fixed. *2: when setting it to 4mhz by trimming. 61 fujitsu semiconductor confidential r2.1 ds706-00007-1v0-e mb9b100 series 2. pin characteristics (vcc = avcc = 2.7v to 5.5v, vss = avss = 0v ta = - 40 ? c to + 85 ? c) value parameter symbol pin name conditions min typ max unit remarks "h" level input voltage (hysteresis input) v ihs cmos hysteresis input pin, md0,1 - vcc 0.8 - vcc + 0.3 v "l" level input voltage (hysteresis input) v ils cmos hysteresis input pin, md0,1 - vss - 0.3 - vcc 0.2 v vcc ? 4.5 v i oh = - 4ma 4ma type vcc < 4.5 v i oh = - 2ma vcc - 0.5 - vcc v vcc ? 4.5 v i oh = - 12ma 12ma type vcc ? 4.5 v i oh = - 8ma vcc - 0.5 - vcc v vcc ? 4.5 v i oh = - 25.3ma "h" level output voltage v oh p80, p81 vcc < 4.5 v i oh = - 13.4ma vcc - 0.4 - vcc v vcc ? 4.5 v i ol = 4ma 4ma type vcc < 4.5 v i ol = 2ma vss - 0.4 v vcc ? 4.5 v i ol = 12ma 12ma type vcc ? 4.5 v i ol = 8ma vss - 0.4 v vcc ? 4.5 v i ol = 19.7ma "l" level output voltage v ol p80, p81 vcc < 4.5 v i ol = 11.9ma vss - 0.4 v input leak current i il - - - 5 - 5 a vcc ? 4.5 v 25 50 100 pull-up resistance value r pu pull-up pin vcc ? 4.5 v 30 80 200 k ? input capacitance c in other than vcc, vss, a vcc, avss, av r h - - 5 15 pf 62 fujitsu semiconductor confidential r2.1 ds706-00007-1v0-e mb9b100 series ? ac characteristics the following tables show the ac characteristics. (1) main clock input characteristics (vcc = 2.7v to 5.5v, vss = 0v ta = - 40 ? c to + 85 ? c) value parameter symbol pin name conditions min max unit remarks vcc ? 4.5v 4 48 vcc ? 4.5v 4 20 mhz when crystal oscillator is connected vcc ? 4.5v 4 48 input frequency f ch vcc ? 4.5v 4 20 mhz when using external clock vcc ? 4.5v 20.83 250 input clock cycle t cylh vcc ? 4.5v 50 250 ns when using external clock input clock pulse width - p wh /t cylh p wl /t cylh 45 55 % when using external clock input clock rise time and fall time t cf t cr x0 x1 - - 5 ns when using external clock f cc - - - 80 mhz cpu/ahb bus clock f cp0 - - - 40 mhz peripheral bus clock 0 (apb0) f cp1 - - - 40 mhz peripheral bus clock 1 (apb1) internal operating clock frequency f cp2 - - - 40 mhz peripheral bus clock 1 (apb2) t cycc - - 12.5 - ns cpu/ahb bus clock t cycp0 - - 25 - ns peripheral bus clock 0 (apb0) t cycp1 - - 25 - ns peripheral bus clock 1 (apb1) internal operating clock cycle time t cycp2 - - 25 - ns peripheral bus clock 1 (apb2) 0.8vcc 0.8vcc 0.8vcc t cylh x0 p wh 0.2vcc t cf p wl t cr 0.2vcc 63 fujitsu semiconductor confidential r2.1 ds706-00007-1v0-e mb9b100 series (2) sub clock input characteristics (vcc = 2.7v to 5.5v, vss = 0v ta = - 40 ? c to + 85 ? c) value parameter symbol pin name conditions min typ max unit remarks - - 32.768 - khz when crystal oscillator is connected input frequency f cl - 32 - 100 khz when using external clock input clock cycle t cyll - 10 - 31.25 s when using external clock input clock pulse width - x0a x1a p wh /t cyll p wl /t cyll 45 - 55 % when using external clock 0.8vcc 0.8vcc 0.8vcc t cyll x0a p wh 0.2vcc p wl 0.2vcc (3) built-in cr oscillation characteristics ? built-in high-speed cr (vcc = 2.7v to 5.5v, vss = 0v ta = - 40 ? c to + 85 ? c) value parameter symbol conditions min typ max unit remarks ta = + 25 ? c 3.92 4 4.08 when trimming ta = 0 ? c to + 70 ? c 3.84 4 4.16 ta = - 40 ? c to + 85 ? c 3.8 4 4.2 when trimming clock frequency f crh ta = - 40 ? c to + 85 ? c 3 4 5 mhz when not trimming ? built-in low-speed cr (vcc = 2.7v to 5.5v, vss = 0v ta = - 40 ? c to + 85 ? c) value parameter symbol conditions min typ max unit remarks clock frequency f crl - 50 100 150 khz 64 fujitsu semiconductor confidential r2.1 ds706-00007-1v0-e mb9b100 series 65 fujitsu semiconductor confidential r2.1 (4) operating conditions of pll (vcc = 2.7v to 5.5v, vss = 0v ta = - 40 ? c to + 85 ? c) value parameter symbol min typ max unit remarks pll oscillation stabilization wait time (lock up time)* t lock 100 - - s pll input clock frequency f plli 4 - 30 mhz pll multiple rate - 4 - 30 multiple pll macro oscillation clock frequency f pllo 60 - 120 mhz *: time from when the pll starts operating until the oscillation stabilizes. (5) reset input characteristics (vcc = 2.7v to 5.5v, vss = 0v ta = - 40 ? c to + 85 ? c) value parameter symbol pin name conditions min max unit remarks reset input time t initx initx - 500 - ns (6) power-on reset timing (vcc = 2.7v to 5.5v, vss = 0v ta = - 40 ? c to + 85 ? c) value parameter symbol pin name min max unit remarks power supply rising time tr 0 - ms power supply shut down time toff vcc 1 - ms 0.2v 2.7v tr to ff 0.2v 0.2v vcc ds706-00007-1v0-e mb9b100 series (7) external bus timing ? asynchronous sram mode (vcc = 2.7v to 5.5v, vss = 0v ta = - 40 ? c to + 85 ? c) value parameter symbol pin name conditions min max unit remarks vcc ? 4.5v moex min pulse width t oew moex vcc ? 4.5v t hclk 1 - 3 - ns vcc ? 4.5v 0 10 moex ? ? address delay time t oel - av moex mad24 to 00 vcc ? 4.5v 0 20 ns vcc ? 4.5v 0 10 moex ? ? address delay time t oeh - ax moex mad24 to 00 vcc ? 4.5v 0 20 ns vcc ? 4.5v moex ? ? mcsx ? delay time t oel - csl moex mcsx vcc ? 4.5v 0 10 ns vcc ? 4.5v moex ? ? mcsx ? delay time t oeh - csh moex mcsx vcc ? 4.5v 0 10 ns vcc ? 4.5v 20 - data set up ? moex ? time t ds - oe moex mdata15 to 0 vcc ? 4.5v 38 - ns vcc ? 4.5v moex ? ? data hold time t dh - oe moex mdata15 to 0 vcc ? 4.5v 0 - ns vcc ? 4.5v t hclk 1 - 5 - mcsx ? ? mwex ? delay time t csl - wel mcsx mwex vcc ? 4.5v t hclk 1 - 10 - ns vcc ? 4.5v t hclk 1 - 5 - mwex ? ? mcsx ? delay time t weh - csh mcsx mwex vcc ? 4.5v t hclk 1 - 10 - ns vcc ? 4.5v t hclk 1 - 5 - address ? mwex ? delay time t av - w e l mwex mad24 to 00 vcc ? 4.5v t hclk 1 - 15 - ns vcc ? 4.5v t hclk 1 - 5 - mwex ? ? address delay time t weh - ax mwex mad24 to 00 vcc ? 4.5v t hclk 1 - 15 - ns vcc ? 4.5v 0 5 mwex ? ? mdqm ? delay time t wel - dqml mwex mdqm0 to 1 vcc ? 4.5v 0 10 ns vcc ? 4.5v 0 5 mwex ? ? mdqm ? delay time t weh - dqmh mwex mdqm0 to 1 vcc ? 4.5v 0 10 ns vcc ? 4.5v mwex min pulse width t wew mwex vcc ? 4.5v t hclk 1 - 3 - ns vcc ? 4.5v - 5 5 mwex ? ? data delay time t wel - dv mwex mdata15 to 0 vcc ? 4.5v -15 15 ns vcc ? 4.5v t hclk 1 - 5 - mwex ? ? data delay time t weh - dx mwex mdata15 to 0 vcc ? 4.5v t hclk 1 - 15 - ns note: when the external load capacitance = 50pf. 66 fujitsu semiconductor confidential r2.1 ds706-00007-1v0-e mb9b100 series (continued) v il v ih v oh mcsx0 to 7 mad24 to 00 moex m data15 to 0 t oew v ol v ol v oh t oe l- av v ol v oh t oel-csl v ol v oh v ih v il t ds-oe t dh-oe t oeh-ax read sram read hclk t cyc v oh v oh t oeh-csh mw ex m data15 to 0 v oh v ol v ol v oh write mcsx0 to 7 m ad24 to 00 v ol v ol v oh v ol v oh sram write hclk t cyc v oh m dqm 0 to 1 v oh t wel-dqml v ol v ol v oh t w eh-dx t weh-ax t csl-w el t wew t w eh-csh t w eh-dqmh t wel-dv t av-w el 67 fujitsu semiconductor confidential r2.1 ds706-00007-1v0-e mb9b100 series ? nand flash mode (vcc = 2.7v to 5.5v, vss = 0v ta = - 40 ? c to + 85 ? c) value parameter symbol pin name conditions min max unit remarks vcc ? 4.5v mnrex min pulse width t nrew mnrex vcc ? 4.5v t hclk 1 - 3 - ns vcc ? 4.5v 20 - data set up ? mnrex ? tiime t ds - nre mnrex mdata15 to 0 vcc ? 4.5v 38 - ns vcc ? 4.5v 0 - mnrex ? ? data hold time t dh - nre mnrex mdata15 to 0 vcc ? 4.5v 0 - ns vcc ? 4.5v t hclk 1 - 5 - mnale ? ? mnwex delay time t aleh - nwel mnale mnwex vcc ? 4.5v t hclk 1 - 15 - ns vcc ? 4.5v t hclk 1 - 5 - mnwex ? ? mnale delay time t nweh - alel mnale mnwex vcc ? 4.5v t hclk 1 - 15 - ns vcc ? 4.5v t hclk 1 - 5 - mncle ? ? mnwex delay time t cleh - nwel mncle mnwex vcc ? 4.5v t hclk 1 - 15 - ns vcc ? 4.5v t hclk 1 - 5 - mnwex ? ? mncle delay time t nweh - clel mncle mnwex vcc ? 4.5v t hclk 1 - 15 - ns vcc ? 4.5v mnwex min pulse width t nwew mnwex vcc ? 4.5v t hclk 1 - 3 - ns vcc ? 4.5v - 5 + 5 mnwex ? ? data delay time t nwel - dv mnwex mdata15 to 0 vcc ? 4.5v -15 +15 ns vcc ? 4.5v t hclk 1 - 5 - mnwex ? ? data delay time t nweh - dx mnwex mdata15 to 0 vcc ? 4.5v t hclk 1 - 15 - ns note: when the external load capacitance = 50pf. 68 fujitsu semiconductor confidential r2.1 ds706-00007-1v0-e mb9b100 series (continued) v il v ih mnrex mdata15 to 0 v ol v oh v ih v il t ds-nre t dh-nr e read nand flash read t nrew hclk t cyc v oh v oh mdata15 to 0 v oh v ol v ol v oh write n an d f las h wr ite hclk t cyc mnwex v oh v ol t nw ew v ol v oh t nw eh-dx v oh v ol mncle mnale t aleh-nw el t nw el-dv t nw eh-alel t cleh-nw el t nw eh - c lel 69 fujitsu semiconductor confidential r2.1 ds706-00007-1v0-e mb9b100 series (8) base timer input timing ? timer input timing (vcc = 2.7v to 5.5v, vss = 0v ta = - 40 ? c to + 85 ? c) value parameter symbol pin name conditions min max unit remarks input pulse width t tiwh t tiwl tioan/tiobn (when using as eck,tin) - 2t cycp - ns v ihs v ils eck tin t tiw h v ihs v ils t tiw l ? trigger input timing (vcc = 2.7v to 5.5v, vss = 0v ta = - 40 ? c to + 85 ? c) value parameter symbol pin name conditions min max unit remarks input pulse width t trgh t trgl tioan/tiobn (when using as tgin) - 2t cycp - ns v ihs v ils tgin t trg h v ihs v ils t trg l 70 fujitsu semiconductor confidential r2.1 ds706-00007-1v0-e mb9b100 series (9) uart timing ? synchronous serial (spi = 0, scinv = 0) (vcc = 2.7v to 5.5v, vss = 0v ta = - 40 ? c to + 85 ? c) vcc ? 4.5v vcc ? 4.5v parameter symbol pin name conditions min max min max unit serial clock cycle time tscy c sckx 4tcycp - 4tcycp - ns sck ? ? sot delay time tslovi sckx sotx -30 +30 - 20 + 20 ns sin ? sck ? setup time tivshi sckx sinx 50 - 30 - ns sck ? ? sin hold time tshixi sckx sinx internal shift clock operation 0 - 0 - ns serial clock "l" pulse width tslsh sckx 2tcycp - 10 - 2tcycp - 10 - ns serial clock "h" pulse width tshsl sckx tcycp + 10 - tcycp + 10 - ns sck ? ? sot delay time tslove sckx sotx - 50 - 30 ns sin ? sck ? setup time tivshe sckx sinx 10 - 10 - ns sck ? ? sin hold time tshixe sckx sinx 20 - 20 - ns sck fall time tf sckx - 5 - 5 ns sck rise time tr sckx external shift clock operation - 5 - 5 ns notes: ? the above characteristics apply to clk synchronous mode. ? t cycp indicates the peripheral clock cycle time. ? these characteristics only guarantee the same relocate port number. for example, the combination of sclkx_0 and sotx_1 is not guaranteed. ? when the external load capacitance = 50pf. 71 fujitsu semiconductor confidential r2.1 ds706-00007-1v0-e mb9b100 series sck sot sin ms b it= 0 t scy c vol vo h tslovi tiv sh i tsh ixi vi h vi l v oh v ol v ih v il sck sot sin ms bit=1 ts lsh vil vih t slove tiv sh e tsh ixe vi h vi l voh vol tsh sl tr tf v ih vi l v ih vil 72 fujitsu semiconductor confidential r2.1 ds706-00007-1v0-e mb9b100 series ? synchronous serial(spi = 0, scinv = 1) (vcc = 2.7v to 5.5v, vss = 0v ta = - 40 ? c to + 85 ? c) vcc ? 4.5v vcc ? 4.5v parameter symbol pin name conditions min max min max unit serial clock cycle time ts cyc sckx 4tcycp - 4tcycp - ns sck ? ? sot delay time tshovi sckx sotx -30 +30 - 20 + 20 ns sin ? sck ? setup time tivsli sckx sinx 50 - 30 - ns sck ? ? sin hold time tslixi sckx sinx internal shift clock operation 0 - 0 - ns serial clock "l" pulse width tslsh sckx 2tcycp - 10 - 2tcycp - 10 - ns serial clock "h" pulse width tshsl sckx tcycp + 10 - tcycp + 10 - ns sck ? ? sot delay time tshove sckx sotx - 50 - 30 ns sin ? sck ? setup time tivsle sckx sinx 10 - 10 - ns sck ? ? sin hold time tslixe sckx sinx 20 - 20 - ns sck fall time tf sckx - 5 - 5 ns sck rise time tr sckx external shift clock operation - 5 - 5 ns notes: ? the above characteristics apply to clk synchronous mode. ? t cycp indicates the peripheral clock cycle time. ? these characteristics only guarantee the same relocate port number. for example, the combination of sclkx_0 and sotx_1 is not guaranteed. ? when the external load capacitance = 50pf. 73 fujitsu semiconductor confidential r2.1 ds706-00007-1v0-e mb9b100 series sck sot sin ms bit=0 tsc yc vol vo h t sho vi t ivs li ts lix i vih vil voh vol vih vil sck sot sin ms bit=1 ts hsl v il vih tsh ov e tiv sl e t sli xe v oh tsl sh tf tr v il vi h vi l 74 fujitsu semiconductor confidential r2.1 ds706-00007-1v0-e mb9b100 series ? synchronous serial(spi = 1, scinv = 0) (vcc = 2.7v to 5.5v, vss = 0v ta = - 40 ? c to + 85 ? c) vcc ? 4.5v vcc ? 4.5v parameter symbol pin name conditions min max min max unit serial clock cycle time ts cyc sckx 4tcycp - 4tcycp - ns sck ? ? sot delay time tshovi sckx sotx -30 +30 - 20 + 20 ns sin ? sck ? setup time tivsli sckx sinx 50 - 30 - ns sck ? ? sin hold time tslixi sckx sinx 0 - 0 - ns sot ? sck ? delay time tsovli sckx sotx internal shift clock operation 2tcycp - 30 - 2tcycp - 30 - ns serial clock "l" pulse width tslsh sckx 2tcycp - 10 - 2tcycp - 10 - ns serial clock "h" pulse width tshsl sckx tcycp + 10 - tcycp + 10 - ns sck ? ? sot delay time tshove sckx sotx - 50 - 30 ns sin ? sck ? setup time tivsle sckx sinx 10 - 10 - ns sck ? ? sin hold time tslixe sckx sinx 20 - 20 - ns sck fall time tf sckx - 5 - 5 ns sck rise time tr sckx external shift clock operation - 5 - 5 ns notes: ? the above characteristics apply to clk synchronous mode. ? t cycp indicates the peripheral clock cycle time. ? these characteristics only guarantees the same relocate port number. for example, the combination of sclkx_0 and sotx_1 is not guaranteed. ? when the external load capacitance = 50pf. 75 fujitsu semiconductor confidential r2.1 ds706-00007-1v0-e mb9b100 series sck sot sin t sls h v ih v il vil ts hove voh vol tiv sle vih vil vi h vi l ts lixe voh vo l f vih tr v il *2 : c hang es when wr itin g to td r r egis ter *2 ms bit=1 vi h tshs l sck sot sin ts cyc voh v ol vol t shov i vo h vo l t ivsl i vih vil vih vil t sli xi vo h vo l tsovli ms bit=0 76 fujitsu semiconductor confidential r2.1 ds706-00007-1v0-e mb9b100 series ? synchronous serial(spi = 1, scinv = 1) (vcc = 2.7v to 5.5v, vss = 0v ta = - 40 ? c to + 85 ? c) vcc ? 4.5v vcc ? 4.5v parameter symbol pin name conditions min max min max unit serial clock cycle time ts cyc sckx 4tcycp - 4tcycp - ns sck ? ? sot delay time tslovi sckx sotx -30 +30 - 20 + 20 ns sin ? sck ? setup time tivshi sckx sinx 50 - 30 - ns sck ? ?? sin hold time tshixi sckx sinx 0 - 0 - ns sot ? sck ? delay time tsovhi sckx sotx internal shift clock operation 2tcycp - 30 - 2tcycp - 30 - ns serial clock "l" pulse width tslsh sckx 2tcycp - 10 - 2tcycp - 10 - ns serial clock "h" pulse width tshsl sckx tcycp + 10 - tcycp + 10 - ns sck ? ? sot delay time tslove sckx sotx - 50 - 30 ns sin ? sck ? setup time tivshe sckx sinx 10 - 10 - ns sck ? ? sin hold time tshixe sckx sinx 20 - 20 - ns sck fall time tf sckx - 5 - 5 ns sck rise time tr sckx external shift clock operation - 5 - 5 ns notes: ? the above characteristics apply to clk synchronous mode. ? t cycp indicates the peripheral clock cycle time. ? these characteristics only guarantee the same relocate port number. for example, the combination of sclkx_0 and sotx_1 is not guaranteed. ? when the external load capacitance = 50pf. 77 fujitsu semiconductor confidential r2.1 ds706-00007-1v0-e mb9b100 series 78 fujitsu semiconductor confidential r2.1 sck sot sin tscyc vol voh voh i voh vol tivshi vih vil vih vil tshixi voh vol tsov hi t slovi sck sot sin ts hsl vil vih vih i voh vol vih vil vih vil tshixe voh vol t slove tr tslsh tf ms bit=0 ms bit =1 ti vshe ? external clock(ext = 1) : asynchronous only (vcc = 2.7v to 5.5v, vss = 0v ta = - 40 ? c to + 85 ? c) parameter symbol conditions min max unit remarks serial clock "l" pulse width tslsh tcycp + 10 - ns serial clock "h" pulse width tshsl tcycp + 10 - ns sck fall time tf - 5 ns sck rise time tr cl = 50pf - 5 ns sck tshsl vil vih vih tr tslsh tf vil vih vil ds706-00007-1v0-e mb9b100 series (10) external input timing (vcc = 2.7v to 5.5v, vss = 0v ta = - 40 ? c to + 85 ? c) value parameter symbol pin name conditions min max unit remarks adtg a/d converter trigger input frckx free-run timer input clock icxx - 2t cycp *1 - ns input capture dttixx - 2t cycp *1 - ns wave form generator - 2t cycp + 100 *1 - ns input pulse width t inh t inl int00 to int15, nmix 500 *2 - ns external interrupt nmi *1 : t cycp indicates the peripheral clock cycle time except stop when in stop mode. *2 : when in stop mode, in timer mode. t inh v ils v ihs v ihs v ils t inl 79 fujitsu semiconductor confidential r2.1 ds706-00007-1v0-e mb9b100 series (11) quadrature position/revolution counter timing (vcc = 2.7v to 5.5v, vss = 0v ta = - 40 ? c to + 85 ? c) value parameter symbol conditions min max unit ain pin "h" width tahl - ain pin "l" width tall - bin pin "h" width tbhl - bin pin "l" width tbll - bin rise time from ain pin "h" level taubu pc_mode2 or pc_mode3 ain fall time from bin pin "h" level tbuad pc_mode2 or pc_mode3 bin fall time from ain pin "l" level tadbd pc_mode2 or pc_mode3 ain rise time from bin pin "l" level tbdau pc_mode2 or pc_mode3 ain rise time from bin pin "h" level tbuau pc_mode2 or pc_mode3 bin fall time from ain pin "h" level taubd pc_mode2 or pc_mode3 ain fall time from bin pin "l" level tbdad pc_mode2 or pc_mode3 bin rise time from ain pin "l" level tadbu pc_mode2 or pc_mode3 zin pin "h" width tzhl qcr:cgsc="0" zin pin "l" width tzll qcr:cgsc="0" ain/bin rise and fall time from determined zin level tzabe qcr:cgsc="1" determined zin level from ain/bin rise and fall time tabez qcr:cgsc="1" 2t cycp * - ns * : t cycp indicates the peripheral clock cycle time except stop when in stop mode. tahl taubu tbuad tbll tbhl tbdau tadbd bin ain tall 80 fujitsu semiconductor confidential r2.1 ds706-00007-1v0-e mb9b100 series tabez zin tzabe ain/bin tzll zin tzhl tbhl tbuau taubd tall tahl tadbu tbdad ain bin tbll 81 fujitsu semiconductor confidential r2.1 ds706-00007-1v0-e mb9b100 series 82 fujitsu semiconductor confidential r2.1 (12) i 2 c timing (vcc = 2.7v to 5.5v, vss = 0v ta = - 40 ? c ? to + 85 ? c ? ) typical mode high-speed mode parameter symbol conditions min max min max unit remarks scl clock frequency fscl 0 100 0 400 khz (repeated) start condition hold time sda ? ? scl ? thdsta 4.0 - 0.6 - s sclclock "l" width tlow 4.7 - 1.3 - s sclclock "h" width thigh 4.0 - 0.6 - s (repeated) start setup time scl ? ? sda ? tsusta 4.7 - 0.6 - s data hold time scl ? ? sda ? ? thddat 0 3.45 (*2) 0 0.9 (*3) s data setup time sda ? ? ? scl ? tsudat 250 - 100 - ns stop condition setup time scl ? ? sda ? tsusto 4.0 - 0.6 - s bus free time between "stop condition" and "start condition" tbuf cl = 50pf, r = (vp/i ol ) (*1) 4.7 - 1.3 - s noise filter tsp - 2 t cycp (*4) - 2 t cycp (*4) - ns *1 : r and c represent the pull-up re sistance and load capacitance of the scl and sda lines, respectively. vp indicates the power supply voltage of the pull-up resistance and i ol indicates v ol guaranteed current. *2 : the maximum thddat must satisfy that it doesn' t extend at least "l" period (tlow) of device's scl signal. *3 : a high-speed mode i 2 c bus device can be used on a standard mode i 2 c bus system as long as the device satisfies the requirement of "tsudat 250 ns". *4 : t cycp is the peripheral clock cycle time. to use i 2 c, set the peripheral bus clock at 8 mhz or more. sda scl thdsta tlow thddat tsudat thigh tsusta thdsta tsp tbuf tsusto ds706-00007-1v0-e mb9b100 series (13) etm timing (vcc = 2.7v to 5.5v, vss = 0v ta = - 40 ? c to + 85 ? c) value parameter symbol pin name conditions min max unit remarks vcc ? 4.5v 2 9 data hold t etmh traceclk traced3 - 0 vcc ? 4.5v 2 15 ns note: when the external load capacitance = 50pf. v oh v ol v ol v oh hclk t cyc traceclk t etmh v oh v ol v oh t etmh traced3-0 83 fujitsu semiconductor confidential r2.1 ds706-00007-1v0-e mb9b100 series (14) jtag timing (vcc = 2.7v to 5.5v, vss = 0v ta = - 40 ? c to + 85 ? c) value parameter symbol pin name conditions min max unit remarks vcc ? 4.5v tms,tdi setup time t jtags tck tms,tdi vcc ? 4.5v 15 - ns vcc ? 4.5v tms,tdi hold time t jtagh tck tms,tdi vcc ? 4.5v 15 - ns vcc ? 4.5v - 25 tdo delay time t jtagd tck tdo vcc ? 4.5v - 45 ns note: when the external load capacitance = 50pf. v ol v oh tck tms/tmi t jtagd tdo v ol v oh v ol v oh t jtag s v ol v oh t jtag h 84 fujitsu semiconductor confidential r2.1 ds706-00007-1v0-e mb9b100 series ? 12bit a/d converter this chapter shows the electrical ch aracteristics for the a/d converter. 1. electrical characteristics for the a/d converter. (vcc = avcc = 2.7v to 5.5v, vss = avss = 0v ta = - 40 ? c to + 85 ? c) value parameter pin name min typ max unit remarks resolution - - - 12 bit linearity error - - 4.5 - + 4.5 lsb differential linearity error - -2.5 - + 2.5 lsb zero transition voltage an0 to an15 - 20 - + 20 mv full transition voltage an0 to an15 - 20 - + 20 mv avrh = 2.7v to 5.5v conversion time - 1.0 (*1) - - s avcc ? 4.5v *2 - - avcc ? 4.5v sampling time ts *2 - - ns avcc < 4.5v 55.5 avcc ? 4.5v compare clock cycle *3 tcck 166.7 - 10000 ns avcc < 4.5v state transition time to operation permission tstt 2.5 - - s - 2.3 3.6 ma a/d 1unit operation power supply current (analog + digital) avcc - 0.1 2 a when xstb is 0 (3unit) - 2.2 3.0 ma a/d 1unit operation av r h = 5 . 5 v reference power supply current (between avrh to av s s ) av r h - 0.03 0.6 a when xstb is 0 (3unit) analog input capacity cin - - 14.5 pf 0.93 avcc ? 4.5v analog input resistance rin - - 2.04 k ? avcc < 4.5v interchannel disparity - - - 4 lsb analog port input current an0 to an15 - - 5 a analog input voltage an0 to an15 av s s - av r h v reference voltage avrh avss - avcc v *1: conversion time is the value of sampling time(ts) + compare time(tc). the condition of the minimum conversion time is when hclk=72mhz, the value of sampling time: 0.222 s, the value of sampling time: 778ns (avcc ? 4.5v) ensure that it satisfies the value of sampli ng time(ts) and compare clock cycle (tcck). for setting of sampling time and compare clock cycle, see chapter "12-bit a/d converter" in "peripheral manual". *2: a necessary sampling time changes by external impedance. ensure that it set the sampling time to satisfy (equation 1) *3: compare time (tc) is the value of (equation 2) 85 fujitsu semiconductor confidential r2.1 ds706-00007-1v0-e mb9b100 series (continued) rin re xt cin comparator an0 to an15 analog in put pi n analog signal source (equ at ion 1) ts ? ( rin + rext ) cin 9 ts : sampling time rin : input resistance of a/d = 0.93k ? 4.5 ? avcc ? 5.5 input resistance of a/d = 2.04k ? 2.7 ? avcc < 4.5 cin : input capacity of a/d = 14.5pf 2.7 ? avcc ? 5.5 rext : output impedance of external circuit (equation 2) tc = tcck 14 tc : compare time tcck : comrare clock cycle 86 fujitsu semiconductor confidential r2.1 ds706-00007-1v0-e mb9b100 series ? definition of 12-bit a/d converter terms ? resolution : analog variation that is recognized by an a/d converter. ? linearity error : deviation of the line between the zero-transition point (0b000000000000 ?? 0b000000000001) and the full-scale transition point (0b111111111110 ?? 0b111111111111) from the actual conversion characteristics. ? differential linearity error : deviation from the ideal valu e of the input voltage that is required to change the output code by 1 lsb. v nt - {1lsb (n - 1) + v ot } linearity error of digital output n = 1lsb [lsb] v (n + 1) t - v nt differential linearity error of digital output n = 1lsb - 1 [lsb] v fst - v ot 1lsb = 4094 n : a/d converter digital output value. v ot : voltage at which the digital output changes from 0x000 to 0x001. v fst : voltage at which the digital output changes from 0xffe to 0xfff. v nt : voltage at which the digital output changes from 0x(n 1) to 0xn. linearity error differential linearity error digital output digital output a ctual conversion characteristics actual conversion characteristics ideal characteristics (actually- measured value) a ctual conversion characteristics a ctual conversion characteristics (actually-measured value) (actually-measured value) ideal characteristics (actually-measured value) analog input analog input (actually-measured value) 0x001 0x002 0x003 0x004 0xffd 0xffe 0xfff avss avrh avss avrh 0x(n-2) 0x(n-1) 0x(n+1) 0xn {1 lsb(n-1) + v ot } v nt v fst v ot v nt v (n+1)t 87 fujitsu semiconductor confidential r2.1 ds706-00007-1v0-e mb9b100 series ? low voltage detection characteristics 1. low voltage detection reset (ta = - 40 ? c to + 85 ? c) value parameter symbol conditions min typ max unit remarks detected voltage vdl - 2.20 2.40 2.60 v when voltage drops released voltage vdh - 2.30 2.50 2.70 v when voltage rises 2. interrupt of low voltage detection (ta = - 40 ? c to + 85 ? c) value parameter symbol conditions min typ max unit remarks detected voltage vdl 2.58 2.8 3.02 v when voltage drops released voltage vdh svhi = 0000 2.67 2.9 3.13 v when voltage rises detected voltage vdl 2.76 3.0 3.24 v when voltage drops released voltage vdh svhi = 0001 2.85 3.1 3.34 v when voltage rises detected voltage vdl 2.94 3.2 3.45 v when voltage drops released voltage vdh svhi = 0010 3.04 3.3 3.56 v when voltage rises detected voltage vdl 3.31 3.6 3.88 v when voltage drops released voltage vdh svhi = 0011 3.40 3.7 3.99 v when voltage rises detected voltage vdl 3.40 3.7 3.99 v when voltage drops released voltage vdh svhi = 0100 3.50 3.8 4.10 v when voltage rises detected voltage vdl 3.68 4.0 4.32 v when voltage drops released voltage vdh svhi = 0111 3.77 4.1 4.42 v when voltage rises detected voltage vdl 3.77 4.1 4.42 v when voltage drops released voltage vdh svhi = 1000 3.86 4.2 4.53 v when voltage rises detected voltage vdl 3.86 4.2 4.53 v when voltage drops released voltage vdh svhi = 1001 3.96 4.3 4.64 v when voltage rises lvd stabilization wait time t lvd w - - - 2040 tcycp * s * : t cycp indicates the peripheral clock cycle time. dt dv vdh time voltage vdl vcc 88 fujitsu semiconductor confidential r2.1 ds706-00007-1v0-e 89 fujitsu semiconductor confidential r2.1 mb9b100 series ? flash memory write/erase characteristics (vcc = 2.7v to 5.5v, ta = - 40 ? c to + 85 ? c) value parameter min typ max value remarks large sector 0.6 3.1 sector erase time small sector - 0.3 1.6 s excludes write time prior to internal erase half word (16 bit) write time - 25 400 s not including system-level overhead time. chip erase time - 7.2 37.6 s excludes write time prior to internal erase erase/write cycles and data hold time erase/write cycles (cycle) data hold time (year) remarks 1,000 20 * 10,000 10 * 100,000 5 * *: this value comes from the technology qualification (using arrhenius equation to translate high temperature measurements into normalized value at + 85 ? c) . ds706-00007-1v0-e mb9b100 series ? example of characteristic power supply current (pll run mode, pll sleep mode) icc normal operation(pll) temperature characteristics vcc:5.5v, cpu:80mh, peripheral:40mh,flash 2wait 0 10 20 30 40 50 60 70 80 90 100 110 120 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 temperature ta[ ] power supply current [ma] iccs sleep operation(pll) temperature characteristics vcc:5.5v, peripheral:40mh 0 10 20 30 40 50 60 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 temperature ta[ ] power supply current [ma] power supply current (sub run mode) icc normal operation(sub oscillation) temperature characteristics vcc:5.5v, cpu/peripheral:32khz 0 50 100 150 200 250 300 350 400 450 500 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 temperature ta[] power supply current [a] icc normal operation(sub oscillation) temperature characteristics(semi-log) vcc:5.5v, cpu/peripheral:32khz 1 10 100 1000 -40-30-20-100 1020304050607080 temperature ta[] power supply current [a] (log) power supply current (sub sleep mode) iccs sleep operation(sub oscillation) temperature characteristics vcc:5.5v, peripheral:32khz 0 50 100 150 200 250 300 350 400 450 500 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 temperature ta[] power supply current [a] iccs sleep operation(sub oscillation) temperature characteristics(semi-log) vcc:5.5v, peripheral:32khz 1 10 100 1000 -40-30-20-100 1020304050607080 temperature ta[] power supply current [a] (log) 90 fujitsu semiconductor confidential r2.1 ds706-00007-1v0-e 91 mb9b100 series power supply current (sub timer mode) i cct timer mode(sub oscillation) temperature characteristics vcc:5.5v, lvd is off 0 50 100 150 200 250 300 350 400 450 500 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 temperature ta[] power supply current [a] i cct timer mode(sub oscillation) temperature characteristics(semi-log) vcc:5.5v, lvd is off 1 10 100 1000 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 temperature ta[] power supply current [a] (log) power supply current (stop mode) i cch stop mode (sub oscillation) temperature characteristics vcc:5.5v, lvd is off 0 50 100 150 200 250 300 350 400 450 500 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 temperature ta[] power supply current [a] i cch stop mode (sub oscillation) temperature characteristics(semi-log) vcc:5.5v, lvd is off 1 10 100 1000 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 temperature ta[] power supply current [a] (log) fujitsu semiconductor confidential r2.1 ds706-00007-1v0-e mb9b100 series ? ordering information part number package mb9bf104npmc plastic ? lqfp(0.5mm pitch),100-pin (fpt-100p-m20*/m23) mb9bf105npmc plastic ? lqfp(0.5mm pitch),100-pin (fpt-100p-m20*/m23) mb9bf106npmc plastic ? lqfp(0.5mm pitch),100-pin (fpt-100p-m20*/m23) mb9bf104rpmc plastic ? lqfp(0.5mm pitch),120-pin (fpt-120p-m21) mb9bf105rpmc plastic ? lqfp(0.5mm pitch),120-pin (fpt-120p-m21) mb9bf106rpmc plastic ? lqfp(0.5mm pitch),120-pin (fpt-120p-m21) mb9bf104nbgl plastic ? pfbga(0.8mm pitch),112-pin (bga-112p-m04) mb9bf105nbgl plastic ? pfbga(0.8mm pitch),112-pin (bga-112p-m04) mb9bf106nbgl plastic ? pfbga(0.8mm pitch),112-pin (bga-112p-m04) * : es product only 92 fujitsu semiconductor confidential r2.1 ds706-00007-1v0-e mb9b100 series 93 fujitsu semiconductor confidential r2.0 ? package dimensions 100-pin plastic lqfp lead pitch 0.50 mm package width package length 14.0 mm 14.0 mm lead shape gullwing sealing method plastic mold mounting height 1.70 mm max weight 0.65 g code (reference) p-lfqfp100-14 14-0.50 100-pin plastic lqfp (fpt-100p-m20) (fpt-100p-m20) c 2005 -2010 fujitsu semiconductor limited f100031s-c-3-5 16.000.20(.630.008)sq 12 5 26 51 76 50 75 100 0.50(.020) 0.200.05 (.008.002) m 0.08(.003) 0.1450.055 (.006.002) 0.08(.003) "a" index .059 ?.004 +.008 ?0.10 +0.20 1.50 (mounting height) 0~8 0.500.20 (.020.008) (.024.006) 0.600.15 0.25(.010) 0.100.10 (.004 .004) details of "a" part (stand off) * 14.000.10(.551.004)sq dimensions in mm (inches). note: the values in parentheses are reference values note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. please check the latest package dimension at the following url. http://edevice.fujitsu.com/package/en-search/ ds706-00007-1v0-e mb9b100 series (continued) 100-pin plastic lqfp lead pitch 0.50 mm package width package length 14.00 mm 14.00 mm lead shape gullwing lead bend direction normal bend sealing method plastic mold mounting height 1.70 mm max weight 0.65 g 100-pin plastic lqfp (fpt-100p-m23) (fpt-100p-m23) c 2009-2010 fujitsu semiconductor limited f100034s-c-3-4 14.000.10(.551 .004)sq 16.000.20(.630 .008)sq 12 5 51 76 75 100 0.50(.020) 0.220.05 (.009.002) m 0.08(.003) * 26 50 0.145 0.055 (.006 .002) 0.08(.003) "a" index 0~8 0.500.20 (.020.008) 0.100.10 (.004.004) details of "a" pa rt (stand off) + .008 +0.20 (mounting height) -0.10 1.50 .059 -.004 ( ) 0.600.15 (.024.006) 0.25(.010) dimensions in mm (inches). note: the values in parentheses are reference values. note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. please check the latest package dimension at the following url. http://edevice.fujitsu.com/package/en-search/ 94 fujitsu semiconductor confidential r2.0 ds706-00007-1v0-e mb9b100 series (continued) 120-pin plastic lqfp lead pitch 0.50 mm package width package length 16.0 16.0 mm lead shape gullwing sealing method plastic mold mounting height 1.70 mm max weight 0.88 g code (reference) p-lfqfp120-16 16-0.50 120-pin plastic lqfp (fpt-120p-m21) (fpt-120p-m21) c 2002-2010 fujitsu semiconductor limited f120033s-c-4-7 1 30 60 31 90 61 120 91 sq 18.000.20(.709.008)sq 0.50(.020) 0.220.05 (.009.002) m 0.08(.003) index .006 ?.001 +.002 ?0.03 +0.05 0.145 "a" 0.08(.003) lead no. .059 ?.004 +.008 ?0.10 +0.20 1.50 details of "a" part (mounting height) 0.600.15 (.024.006) 0.25(.010) (.004.002) 0.100.05 (stand off) 0~8 * .630 ?.004 +.016 ?0.10 +0.40 16.00 dimensions in mm (inches). note: the values in parentheses are reference values. note 1) * : these dimensions do not include resin protrusion. resin protrusion is +0.25(.010) max(each side). note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. please check the latest package dimension at the following url. http://edevice.fujitsu.com/package/en-search/ 95 fujitsu semiconductor confidential r2.0 ds706-00007-1v0-e 96 mb9b100 series (continued) 112-ball plastic pfbga ball pitch 0.80 mm package width package length 10.00 10.00 mm lead shape soldering ball sealing method plastic mold ball size 0.45 mm mounting height 1.45 mm max. weight 0.22 g 112-ball plastic pfbga (bga-112p-m04) (bga-112p-m04) c 2003-2010 fujitsu semiconductor limited b112004s-c-2-3 10.000.10(.394.004) (.049.008) 1.250.20 (seated height) 6 f index (index area) 10.000.10 (.394.004) (112- 0.18.004) 112- 0.45010 0.350.10 (.014.004) (stand off) 0.10(.004) s b a ghjk ledcba 7 8 9 10 11 5 4 3 2 1 0.80(.031) ref ref 0.80(.031) 0.08(.003) b as m 0.20(.008) s b s as 0.20(.008) dimensions in mm (inches). note: the values in parentheses are reference values. please check the latest package dimension at the following url. http://edevice.fujitsu.com/package/en-search/ fujitsu semiconductor confidential r2.0 ds706-00007-1v0-e mb9b100 series ? major changes in this edition page section change results - all added package : lqfp100(fpt-100p-m23). 64 ? electrical characteristics ? ac characteristics (3) built-in cr oscillation characteristics changed the value of " ? built-in high-speed cr". (tbd ? fixed value) 85 ? 12bit a/d converter changed the value and remarks of tcck, avcc, avrh. 90, 91 ? example of characteristic added a new section. 92 ? ordering information added a new section. in the previous revision, the number at the upper-right of the page is ds706-00007-0v01-e. 97 fujitsu semiconductor confidential r2.1 ds706-00007-1v0-e mb9b100 series 98 fujitsu semiconductor confidential r2.0 98 fuj itsu semiconductor confidential r2.0 mb9b100 series ds706-00007-1v0-e mb9b100 series 99 fujitsu semiconductor confidential r2.0 99 fuj itsu semiconductor confidential r2.0 mb9b100 series ds706-00007-1v0-e fujitsu semiconductor limited nomura fudosan shin-yokohama bldg . 10-23, shin-yokohama 2-chome, kohoku-ku yokohama kanagawa 222-0033, japan tel: +81-45-415-5858 http://jp.fujitsu.com/fsl/en/ for further information please contact: north and south america fujitsu semiconductor america, inc. 1250 e. arques avenue, m/s 333 sunnyvale, ca 94085-5401, u.s.a. tel: +1-408-737-5600 fax: +1-408-737-5999 http://us.fujitsu.com/micro/ europe fujitsu semiconductor europe gmbh pittlerstrasse 47, 63225 langen, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://emea.fujitsu.com/semiconductor/ korea fujitsu semiconductor korea ltd. 206 kosmo tower building, 1002 daechi-dong, gangnam-gu, seoul 135-280, republic of korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 http://kr.fujitsu.com/fmk/ asia pacific fujitsu semiconductor asia pte. ltd. 151 lorong chuan, #05-08 new tech park 556741 singapore tel : +65-6281-0770 fax : +65-6281-0220 http://www.fujitsu.com/sg/services/micro/semiconductor/ fujitsu semiconductor shanghai co., ltd. rm. 3102, bund center, no.222 yan an road (e), shanghai 200002, china tel : +86-21-6146-3688 fax : +86-21-6335-1605 http://cn.fujitsu.com/fss/ fujitsu semiconductor pacific asia ltd. 10/f., world commerce centre, 11 canton road, tsimshatsui, kowloon, hong kong tel : +852-2377-0226 fax : +852-2376-3269 http://cn.fujitsu.com/fsp/ specifications are subject to change without notice. for further information please contact each office. all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with sales representatives before ordering. the information, such as descriptions of function and applicatio n circuit examples, in this document are presented solely for t he purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu semiconductor does not warrant proper operation of the device with respect to use based on such informa tion. when you develop equipment incorporat ing the device based on such information, you must assume any re sponsibility arising out of such use of the information. fujitsu semiconductor assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic di agrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent ri ght or copyright, or any other right of fujitsu semiconductor or any third party or does fujitsu semiconductor warrant non-infringement of any third-part y's intellectual property right or other ri ght by using such information. fujitsu semiconductor assumes no liab ility for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, general office use, persona l use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury , severe physical damage or ot her loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile la unch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu semiconductor will not be liable against you and/or any thir d party for any claims or damages aris- ing in connection with above-mentioned uses of the products. any semiconductor devices have an inherent ch ance of failure. you must protect against in jury, damage or loss from such failure s by incorporating safety design measures into your facility a nd equipment such as redundancy, fi re protection, and prevention of over- current levels and other abnormal operating conditions. exportation/release of any products described in this document may require necessary procedures in accordance with the regulati ons of the foreign exchange and foreign trade control law of japan and/or us export control laws. the company names and brand names herein are the trademarks or registered trademarks of their respective owners. edited: sales promotion department |
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